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Re: [Iverilog-devel] Nifty [system verilog] projects
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From: Trevor W. <pha...@gm...> - 2008-05-05 21:23:20
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In addition to supporting interfaces, adding struct/union, enum and typedef support would also be nice. I would consider their inclusion to this task list to be a lower priority as I don't believe that their implementation is quite as simple as increment, decrement, etc. (i.e., I don't believe them to be "low hanging fruit" at this point in IV's development). Trevor On May 5, 2008, at 11:06 AM, Steven Wilson wrote: > Think of Interfaces as a bus that can have tasks included. You may > define alternate versions of the bus (think master and slave > descriptions) allowing source and sink of the bus. You can define > tasks > within the interface description that allow it to be an active part of > the simulation. > > So in one sense it is a very power short-hand method of describing a > design. I can define a bus connection source and sink in a define > file, > then include same in the modules that are using it and just connect > them > with a single interface connection between the port lists at the top > of > the design. > > Steve > > Stephen Williams wrote: >> -----BEGIN PGP SIGNED MESSAGE----- >> Hash: SHA1 >> >> Steven Wilson wrote: >> | In the system verilog arena - I would add Interfaces to the >> descriptions >> | already provided. I suspect that Interfaces is going to be a more >> | challenging effort than always_ff - so I would put it at a second >> tier >> | effort, but this in combo with what has already been proposed >> takes care >> | of most of the things synthesis compatible RTL is going to look >> like! >> >> I admit to not being entirely clear on how interfaces work. Maybe >> when I or any of the other developers gets a good idea how they >> work, we may better judge how they can be integrated in. >> >> I had put SystemVerilog aside for a while because it seemed to be >> getting out of control, but I get the impression it's settling >> down and there's a sense of a practical subset that may be worth >> looking at. I see for example that extended types of SystemVerilog >> are from the Cadence-style proposal that I've been following for >> the Icarus Verilog extended types, so there's already some overlap >> there. >> >> >> - -- >> Steve Williams "The woods are lovely, dark and deep. >> steve at icarus.com But I have promises to keep, >> http://www.icarus.com and lines to code before I sleep, >> http://www.picturel.com And lines to code before I sleep." >> -----BEGIN PGP SIGNATURE----- >> Version: GnuPG v2.0.4-svn0 (GNU/Linux) >> Comment: Using GnuPG with SUSE - http://enigmail.mozdev.org >> >> iD8DBQFIHypyrPt1Sc2b3ikRAnpcAKDm+BaS9BYe8GsHMth4u6aPpf8diQCguZMJ >> ta9Qzds8xZoX3MTTcbC3+Pk= >> =VG9K >> -----END PGP SIGNATURE----- >> >> ------------------------------------------------------------------------- >> This SF.net email is sponsored by the 2008 JavaOne(SM) Conference >> Don't miss this year's exciting event. There's still time to save >> $100. >> Use priority code J8TL2D2. >> http://ad.doubleclick.net/clk;198757673;13503038;p?http://java.sun.com/javaone >> _______________________________________________ >> Iverilog-devel mailing list >> Ive...@li... >> https://lists.sourceforge.net/lists/listinfo/iverilog-devel >> > > > ------------------------------------------------------------------------- > This SF.net email is sponsored by the 2008 JavaOne(SM) Conference > Don't miss this year's exciting event. There's still time to save > $100. > Use priority code J8TL2D2. > http://ad.doubleclick.net/clk;198757673;13503038;p?http://java.sun.com/javaone > _______________________________________________ > Iverilog-devel mailing list > Ive...@li... > https://lists.sourceforge.net/lists/listinfo/iverilog-devel |
