Re: [Iverilog-devel] Verilog to VHDL project setup.

[Cary R. <cy...@ya...>]

--- On Fri, 4/25/08, Stephen Williams <st...@ic...> wrote:

> The ivtest project on sourceforge.net is where we keep the
> Icarus
> Verilog regression test suite. Cary has done the recent big
> work
> on the compiler test harness script (vvp_reg.pl) and also
> other
> harness scripts. He knows perl, I do not:-/ Ideally, we
> should
> integrate your stuff into that project, probably with a
> test
> harness of its own.

This will likely mirror the changes I did to support valgrind testing. Slightly modify the programs that are called to run the tests and possible recode the internal diff routine to ignore any extra stuff from the VHDL simulator. I agree we want this to be a separate program possible vhdl_vvp.pl.

Cary


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