[Iverilog-devel] Verilog to VHDL project setup.

[Stephen W. <st...@ic...>]

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I'm moving this thread to the iverilog-devel mailing list. Others
may have opinions on this subject.

Nick Gasson wrote:
| Stephen Williams wrote:
|>
|>
|> In fact we are going to want to get a few things settled as early
|> as reasonable. One is how you are going to work. In particular, we
|> are going to want to see snapshots and be able to test them in our
|> own build environments.
|>
|> Are you going to create a bit branch? Or deliver your module as
|> an external piece of code? We will probably wind up preferring a
|> git branch, and we'll have to work out the mechanics of that.
|
| I'd prefer a git branch: this should be easiest since I can easily push
| snapshots to the remote repository.

Yes, sounds best. One possibility that I've been thinking of
using you as a guinea pig for is to have you create your own
public clone of the Icarus Verilog repository using one of the
public git hosting services. There is github.com or repo.or.cz.
The latter is older, and I already use it to keep an automatic
mirror of the main repository. (I've been using repo.or.cz as an
automatic mirror host, but it's not been auto-mirroring for the
last few months, so github may be worth a try.)

The idea I have is that you make a public clone, then you create
your branch in that clone and commit and commit and work and
commit to that branch on your clone, and we just "pull" it into
the main repository now and then, or when you are ready.

|>
|> Also, how are you going to test the results? We should see early
|> some Verilog program that we can use as a benchmark of your
|> progress. Ideally, they'll be something we can include in the
|> test suite.
|
| Yes, this is a good idea and will should be one of the first things I
| work on. I'll probably create a bunch of C/C++ unit tests too -- should
| these be integrated with the build / test process? If so, is there a
| preferred framework?

The ivtest project on sourceforge.net is where we keep the Icarus
Verilog regression test suite. Cary has done the recent big work
on the compiler test harness script (vvp_reg.pl) and also other
harness scripts. He knows perl, I do not:-/ Ideally, we should
integrate your stuff into that project, probably with a test
harness of its own.

As for a VHDL simulator, we should pick one that is free and open
source for use by any test harness, if at all possible. There are
ghdl and freehdl (I think ghdl is more active) that we should look
at. I'll ask around on geda-user to see what other people use.


- --
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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