Re: [Iverilog-devel] Path delays simple, conditional and ifnone.

[Cary R. <cy...@ya...>]

--- On Thu, 4/24/08, Stephen Williams <st...@ic...> wrote:
 
> No, order should not be important, and it should collect
> all
> the delay paths. At run time, when the "in" value
> changes,
> all the possible paths are activated. If "cond"
> is true, then
> both in your example are activated. Then the runtime will
> choose the delay that is smallest. In your example, with
> the
> paths not yet annotated, that is clearly 1.5. But if by
> annotation
> the conditional path is given a delay of 1.1, then it will
> be chosen instead.
> 
> If Icarus Verilog does anything other, then it is a bug.
> But I think it gets this right.

OK we have a bug because it is giving different results depending on order!

The attached program gives different delay values depending on the order of the statements as shown the conditional paths are active. If the simple path delay is moved after the conditionals it overrides the value used no matter what.

Cary




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