Re: [Iverilog-devel] Path delays simple, conditional and ifnone.

[Stephen W. <st...@ic...>]

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Cary R. wrote:
| I have started looking at implementing ifnone and in the process I'm
looking at the various delay constructs to see exactly how they work. In
doing this I ran into something that seems very strange. If you have
both a simple path delay and a state dependent path delay. Depending on
the order they appear in the specify block the state dependent delay can
be missed. For example:
|
| (in => out) = 1.5;
| if (cond) (in => out) = 1.8;
|
| will make the delay from in to out 1.8 when the condition is true. If
you swap the order of the statements the delay is always 1.5!
|
| I have not found anything in the spec. that talks about how this
should be resolved. I would expect the simple path delay to act like
ifnone and only fill in cases that are not explicitly covered with a
more specific conditional or it should be flagged as an error since you
are double specifying some of the cases. The only clue implying that
this may be legal is that in the ifnone description it mentions that it
is illegal to specify both an ifnone and a simply (unconditional) module
path. This would imply that ifnone and a simple path delay are identical
in functionality and that we need to make the simple path delay or
ifnone be a default that is used only if you cannot find an active path
in the normal list.
|
| Does the 2005 standard say anything more about this? Thoughts?

Actually, I think your example is perfectly legal and useful.
It is possible to have multiple path delays for a given output,
and in that case, assuming they are all activated at once, the
output delay in use is taken to be the shortest--in this case,
1.5. In fact, in your specific case, it will as you say always
be 1.5 unless SDF annotation changes the simple path delay, which
is a possibility. So although on the surface it seems like a
waste, back annotation can turn it into something important.

(Remember, since all the numbers specified delays can be replaced
by annotation, you can't use the numbers in the Verilog source
to determine the validity of anything.)

If the unconditional path were slower (i.e. 1.9) it would be more
obvious that the conditional path is useful. Then you get the
effect of the simple path acting like an ifnone path. But then
again, if back annotation changes the time to be small, you
are back where you are now.

So I see no problem here. There is a delay selection algorithm
to handle the case of multiple active paths to an output at a
given time.

The ifnone syntax doesn't not allow for there also to be an
identical unconditional path mostly as a matter of syntax.
Ifnone paths are allowed to be without a matching conditional
path, in which case they are treated as an unconditional paths
and will be visible to the SDF annotator as such.

If there are multiple paths that are indistinguishable to the
SDF annotator, then *that* is a problem and the symantics *do*
disallow that. That is the rule to live by.

- --
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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