[Iverilog-devel] Path delays simple, conditional and ifnone.

[Cary R. <cy...@ya...>]

I have started looking at implementing ifnone and in the process I'm looking at the various delay constructs to see exactly how they work. In doing this I ran into something that seems very strange. If you have both a simple path delay and a state dependent path delay. Depending on the order they appear in the specify block the state dependent delay can be missed. For example:

(in => out) = 1.5;
if (cond) (in => out) = 1.8;

will make the delay from in to out 1.8 when the condition is true. If you swap the order of the statements the delay is always 1.5!

I have not found anything in the spec. that talks about how this should be resolved. I would expect the simple path delay to act like ifnone and only fill in cases that are not explicitly covered with a more specific conditional or it should be flagged as an error since you are double specifying some of the cases. The only clue implying that this may be legal is that in the ifnone description it mentions that it is illegal to specify both an ifnone and a simply (unconditional) module path. This would imply that ifnone and a simple path delay are identical in functionality and that we need to make the simple path delay or ifnone be a default that is used only if you cannot find an active path in the normal list.

Does the 2005 standard say anything more about this? Thoughts?

Cary


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