Re: [Iverilog-devel] VVP Performance boots

[Cary R. <cy...@ya...>]

--- On Wed, 4/23/08, Stephen Williams <st...@ic...> wrote:
 
> Yeah, at least post them. I'm curious.

It has been some time since I looked at this. I believe the 0 array index is the aval and the 1 array index is the bval. The basic two input gates have a comparison to see that they are working correctly. The more complex  and single input gates print the output and the s (for the complex gates is this a H/L) value, so if the s output is 1 you need to translate the normal output. The X versions of the gates just put out an x for the H/L case. I left the cmos gate as an exercise for the user ;-). You can verify the result by reading columns left to right from the specification.

Cary


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