Re: [Iverilog-devel] VVP Performance boots

[Cary R. <cy...@ya...>]

--- On Tue, 4/22/08, Stephen Williams <st...@ic...> wrote:

> From: Stephen Williams <st...@ic...>
> Subject: Re: [Iverilog-devel] VVP Performance boots
> To: "Discussions concerning Icarus Verilog development" <ive...@li...>
> Date: Tuesday, April 22, 2008, 5:31 PM
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> 
> Cary R. wrote:
> | --- On Tue, 4/22/08, Stephen Williams
> <st...@ic...> wrote:
> |
> |
> |> We need to look more carefully at the of_ADDI
> instruction.
> |> The
> |> most likely problem is the vector_to_array() call
> returning
> |> a
> |> wrong value.
> |
> | A very good guess! It's actually in
> vvp_vector4_t::subarray() in
> vvp_net.cc. In this case we are getting 32 bits at address
> 32, so on a
> 32 bit machine we are word aligned. The problem is that the
> atmp and
> btmp masking is failing. before the masking we have the
> correct value
> after it we have zero. This is caused by the fact that you
> cannot shift
> a 32 bit value by 32 bits. The same thing could also happen
> with 64 bit
> values. The 100 was a red hearing since it broke the word
> alignment.
> |
> | I will let you decide how you want to fix this. As I
> remember I fixed
> something like this in the exact same routine not too long
> ago. Of
> course that was before you rewrote it to work with the new
> layout ;-)
> 
> 
> Tell me what the attached program does for you on your
> machine.
> When I compile it for 64bit (cc foo.c) and 32bits (cc -m32
> foo.c)
> I get the correct answer. And of course, on PPC32 I get the
> correct
> results. I expect (1<<32) to be 0 on a 32bit machine.
> 
> Still, I'm fixing it here. Try pulling from git.

This is printing:

foo before shift = 0x1
foo after shift = 0x1
foo after subtract = 0x0

The problem as I remember it is that a  bit shift that is greater than or equal to the machine variable width is undefined so in this case it is doing nothing. Though I agree I would also appreciate it if the left shift gave zero for this condition.

Cary


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