Re: [Iverilog-devel] assign/deassign and force/release of bit/part selects.

[Cary R. <cy...@ya...>]

--- Larry Doolittle <ldo...@re...> wrote:
 
> You have to let me assign to a wire.
> All Verilog code that I've seen is full of that construct.

I guess I forgot to mention this is for a procedural assign:

initial begin
  rval = 1'b0;
  #1 assign rval = 1'b1;
  #1 deassign rval;
end

This has nothing to do with a normal continuous assignment which only
works on wires.

Cary


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