Re: [Iverilog-devel] assign/deassign and force/release of bit/part selects.

[Larry D. <ldo...@re...>]

Cary -

On Tue, Apr 08, 2008 at 05:29:01PM -0700, Cary R. wrote:
> The left-hand side of the assignment in the assign statement shall be a
> variable reference or a concatenation of variables. It shall not be a
> memory word (array reference) or a bit-select or a part-select of a
> variable.
> 
> The way I read this is that an assign only works on a register/etc. type
> not a wire (net).

You have to let me assign to a wire.
All Verilog code that I've seen is full of that construct.

   - Larry