[Iverilog-devel] assign/deassign and force/release of bit/part selects.

[Cary R. <cy...@ya...>]

I'm working on the implementation for assign/deassign of bit and part
selects and decided to see what the standard had to say. Very interesting!

For reference this is what it says about assign (section 9.3 page 125
1364-2001):

The left-hand side of the assignment in the assign statement shall be a
variable reference or a concatenation of variables. It shall not be a
memory word (array reference) or a bit-select or a part-select of a
variable.

The way I read this is that an assign only works on a register/etc. type
not a wire (net). The standard say we shouldn't allow an assign to an
array word, but we don't distinguish between individual array words and a
normal variable. Bit and part selects are not allowed, but I'm working on
implementing them.

It says basically the same think for force except it allows force to work
on either variables or nets. Though it is missing the array word
exclusion. 

Can someone look at 2005 and see if it says anything different. Do we
still want this functionality as an enhancement? For now I'm assuming we
do. If nothing else to make force and assign match.

Cary


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