Re: [Iverilog-devel] need a language-lawyer ruling and/or a bug fix

[Cary R. <cy...@ya...>]

--- Larry Doolittle <ldo...@re...> wrote:
 
> The attached code shows a change in behavior in recent
> (as of March 20) git.  It triggered a failure in my
> inverse regression test.  I need to know if my Verilog
> assumptions are wrong, or the new Icarus behavior is wrong.

This does seem to be slightly incorrect. Section 3.6 in 1364-2001 implies
that the initial value should be z, but then the driver value should
propagate. Given that this hasn't happened after #10 implies that the x is
not propagating after the initial z.

For clarity this is how I am thinking things should work.

assign tmp = 1'bx;

should set tmp to x sometime during the first time step.

assign #1 tmp = 1'bx;

should set tmp to x during the 1 time step and tmp is z before that.

Your case is clearly the first case and the x value is not propagating
correctly. This could be a far reaching problem since the basic code in
the patch you referenced is at least conceptually copied from other
places.

Cary


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