[Iverilog-devel] need a language-lawyer ruling and/or a bug fix

[Larry D. <ldo...@re...>]

Guys -

The attached code shows a change in behavior in recent
(as of March 20) git.  It triggered a failure in my
inverse regression test.  I need to know if my Verilog
assumptions are wrong, or the new Icarus behavior is wrong.

iverilog -Wall tern.v -o tern && vvp tern

Used to print out
    x   x
   42  21
But after commit 01eb298228d0adce9d62818e21d47fb274af9060 prints
    x   z
   42  21

  - Larry