Re: [Iverilog-devel] GSoC Proposal Verilog Unit Test

[Cary R. <cy...@ya...>]

--- Rodrigo Peixoto <rod...@gm...> wrote:

> 19            <python_code var="res">lambda a,b: a+b</python_code>

Do you have code that does an implicit sizing of the result or are you
missing a "& 0xfff" in the above equation?

>     a[7:0]     i@|use_mem_file("my_a_memory.mem")

I assume this format precludes the use of random variables since you are
not touching the input vector file.

>     input [15:0] a;

Should these be [7:0] given the previous definitions? My guess is the
[7:0] previously should be [15:0] given the size of the constants.

>From all this I don't see anything that needs to be done to Icarus to
support your test system. I think we are focusing on enhancements to
Icarus itself, not software that uses Icarus. If you are proposing some
enhancements to Icarus I'm missing them, so please explicitly state them.
If Icarus is not processing your output code correctly please submit a bug
report or even better a patch!

Thank you for explaining how your system works.

Cary


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