Re: [Iverilog-devel] GSoC Proposal Verilog Unit Test

[Cary R. <cy...@ya...>]

--- Rodrigo Peixoto <rod...@gm...> wrote:

> The tool is already in alpha version. A lot of features will be
> implemented
> this year until June. For example the random stimulus generation, the
> reference model can will be made in a high level language as Python,
> state
> machine tests and so on.
> 
> This tool could be "integrated" with Icarus. When a developer wants to
> design a module can use this tool to generate the module's skeleton and
> its
> UnitTest (Test Bench) according the rule file (described by the user,
> easy
> and fast).
> 
> Do you think really interesting this project participates of the Google
> Summer of Code?

This is too simple of a description for me to understand exactly what you
are proposing. Can you provide an example with possible some pseudo code
to better explain the process. I would also like to know what type of
rules are available and how the skeleton is specified?

Cary


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