Re: [Iverilog-devel] Draft GSoC proposal

[Cary R. <cy...@ya...>]

Nick,

I agree with Steve this is more than good enough as is to submit. The
following are a few things that you may want to consider. They will
certainly need to be considered during the development phase.

1. The compiler in its currently implementation only has hooks at the end
of the compilation process. The consequence of this is that many
optimizations have been performed on the AST (constant folding,
conditional short circuiting, generate statements processed, etc.).
Because of this we will only be able to do a functional translation. For
example you can determine the value of a Verilog parameter in the code
generator, but you will not find any expressions that reference the
parameter. Is this restriction a problem for useful VHDL code generation?

2. There is still functionality missing from the compiler and runtime.
What is your plan for dealing with this? Is this missing functionality a
problem for the converter? I believe most of the missing functionality
either has a bug report or feature request. We may be able to add some of
this to the compiler and then use code generator checks to protect vvp if
needed.

3. Straight statement conversion is a good start, but keep in mind that
more efficient code can often be generated when looking at certain
combinations of statements (patterns). Are the current code generator
hooks complete enough to perform these type of optimizations?

4. Does it make sense to consider the changes added in 1076-2002?

That's all I came up with for now. Once again great job!

Cary


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