[Iverilog-devel] GSoC Proposal Verilog Unit Test

[Rodrigo P. <rod...@gm...>]

Hi all,

my name is Rodrigo Peixoto, I'm Computer Engineer undergraduate student in
Brazil (UFPE- University Federal of Pernambuco).
Nowadays I'm developing a tool that generates Verilog Unit Tests according
to a rule file.
This is my graduation conclusion work and perhaps will be the theme of my
Master dissertation.

The tool is already in alpha version. A lot of features will be implemented
this year until June. For example the random stimulus generation, the
reference model can will be made in a high level language as Python, state
machine tests and so on.

This tool could be "integrated" with Icarus. When a developer wants to
design a module can use this tool to generate the module's skeleton and its
UnitTest (Test Bench) according the rule file (described by the user, easy
and fast).

Do you think really interesting this project participates of the Google
Summer of Code?


Best Regards,
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Rodrigo José Sarmento Peixoto
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UFPE - CIn ( Engenharia da Computacao )
Skype: rodrigopex
msn: rod...@ho...
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Participante dos projetos:
- HPCIn (Petrobras)
- EriMont (Amadeus)
Projeto de extensão: Inclusão digital escola Padre Machado
Membro do CInLUG: www.cinlug-br.org
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