Re: [Iverilog-devel] Google SoC 2008!

[Nick G. <nm...@yo...>]

Hi all,

I'm interested in working on Icarus Verilog as part of Summer of Code. 
In particular I'm interested in building a VHDL plug-in code generator 
to get a Verilog to VHDL translator (as per the projects wiki). This is 
actually a problem I've encountered in real life -- when I've wanted to 
use Verilog components in a VHDL system. Since it'll be a back-end code 
generator, it should stay clear of a lot of the more complex VHDL 
constructs, so hopefully this will be manageable as a summer project. 
I'd like to focus on getting the synthesisable subset working first, as 
I think this would be the most useful.

I'm a final-year Computer Systems and Software Engineering student at 
the University of York (UK). I've got quite a bit of experience in VHDL 
(mostly designs for Xilinx FPGAs) and the usual C/C++ (I have some 
industrial experience with these). Unfortunately I don't really have any 
Verilog knowledge beyond the usual introduction/tutorials, but I should 
be able to pick it up pretty rapidly (and this project doesn't seem too 
Verilog-y).

If this sounds reasonable I'll have a go at drafting a project proposal. 
Is there anything you're looking for in particular on the application?

I also volunteer to do the git version strings project :-)

Thanks a lot
Nick