Re: [Iverilog-devel] Potential rework of nets/wires support in VVP

[Cary R. <cy...@ya...>]

--- Stephen Williams <st...@ic...> wrote:

> Add to that switch level modeling such as tranif* and rtran*. These
> are odd devices in that they are bidirectional. The resistive
> devices in particular escape me. (I was kinda holding off on resistive
> transistors to see if the problem goes away when AMS support gets
> figured out.)

Once we have multi output gates, or maybe that should be multi inout
gates, implementing these should not be too hard to code. If you were to
do multi output gates I would think implementing a multi output buffer and
one of the rtran gates would be enough to allow someone else to build the
rest. Is it the need or the implementation that is escaping you?

Unless you are hoping that a future version of Verilog-D removes these
gates we still have missing functionality. 
 
> I think that net delays can be understood in term of vvp_net nodes.
> In particular, one can find ways to attach delays between drivers
> of nets and the nets themselves. It may be possible to handle this
> in the elaborator by propagating the net delays to the delays of
> all the driving expressions, but putting a .delay node in place
> is probably the best way of handling it. Specify delays for module
> ports are handled this way.

Basic net delays may be that simple, but the ones from a SDF file are
certainly not. As I remember it, net delays can be unique from any driver
to any receiver, so they cannot be implemented by just inserting simple
delays at the driver and/or receiver. So there are two net delay concepts,
one which is a single constant value specified in the language and the
other is provided in the SDF file which is likely not matched to a net
that was defined to have a net delay in the source Verilog file. To me
this implies that net delays need to be fundamental to the net handling
code.

> Actually, the vvp_net infrastructure inside vvp is probably the
> cleanest and easiest to understand aspect of the vvp runtime:-)

I guess that shows how little I have looked at it.

Cary


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