Re: [Iverilog-devel] Type conversion and parameters

[Stephen W. <st...@ic...>]

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Cary R. wrote:
> In section 4.5.1 of 1364-2001 it states that for non-self-determined
> operands if any operand is real the results will be real, but my
> interpretation of a simple parameter is that it can be self-determined. If
> not specified it takes the type and size of the RHS. So would the
> following give one real and one bit based parameter or two real
> parameters?
> 
> parameter real_val = 1'b1 ? 1.0 : 4'b1010;
> parameter int_val = 1'b0 ? 1.0 : 4'b1010; // is this 4'b1010 or 10.0?

I would say that they are both real. In both cases above, the
operands that carry type in the ternary are both logically checked
for type and width, and I think therefore the ternary as a whole
is real valued. The standard doesn't seem to say so, but I think
it is reasonable to assume that "5.5.1 Rules for expression types"
applies to ternary operators' true and false operands and not
the condition operand (which is defined to be logic):

- From 5.5.1 Rules for expression types:
- -- Expression type depends only on the operands.



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