[Iverilog-devel] preprocessor abuse?

[Larry D. <ldo...@re...>]

Guys -

I'm often tempted to produce patches like the one appended.
I don't know how hostile the reaction will be.  If you don't
like it, just say so.

The advantages include compactness, ease of extension, and
intrinsic self-consistency.  It might also be considered more
opaque and harder to debug, but there are lots of things like
that buried in Icarus, so maybe it doesn't matter.  :-p

This patch doesn't affect the size of the object code.
That can be accomplished with a loop and a data structure,
where the data structure itself uses some preprocessor work.
Untested concept:

struct {bool *flag, const char *name} debug_entry;
struct debug_entry debug_flag_table[]={
#define ENTRY(x) { &debug_##x, #x}
	ENTRY(scopes),
	ENTRY(eval_tree),
	ENTRY(elaborate),
	ENTRY(synth2)
#undef ENTRY
};

   - Larry

--- verilog/main.cc	2008-02-06 15:19:07.000000000 -0800
+++ /home/ldoolitt/src/verilog-0.9/main.cc	2008-02-06 15:42:15.000000000 -0800
@@ -356,20 +356,14 @@
 		  basedir = strdup(cp);
 
 	    } else if (strcmp(buf, "debug") == 0) {
-		  if (strcmp(cp, "scopes") == 0) {
-			debug_scopes = true;
-			cerr << "debug: Enable scopes debug" << endl;
-		  } else if (strcmp(cp,"eval_tree") == 0) {
-			debug_eval_tree = true;
-			cerr << "debug: Enable eval_tree debug" << endl;
-		  } else if (strcmp(cp,"elaborate") == 0) {
-			debug_elaborate = true;
-			cerr << "debug: Enable elaborate debug" << endl;
-		  } else if (strcmp(cp,"synth2") == 0) {
-			debug_synth2 = true;
-			cerr << "debug: Enable synth2 debug" << endl;
-		  } else {
-		  }
+#define DEBUG_FLAG(x) (strcmp(cp, #x) == 0) {debug_##x = true; \
+	cerr << "debug: Enable " #x " debug" << endl;}
+		       if DEBUG_FLAG(scopes)
+		  else if DEBUG_FLAG(eval_tree)
+		  else if DEBUG_FLAG(elaborate)
+		  else if DEBUG_FLAG(synth2)
+		  else { }
+#undef DEBUG_FLAG
 
 	    } else if (strcmp(buf, "depfile") == 0) {
 		  depfile_name = strdup(cp);