Re: [Iverilog-devel] oddity in reproducing pr1879226

[Larry D. <ldo...@re...>]

Steve -

On Wed, Jan 30, 2008 at 09:33:11AM -0800, Stephen Williams wrote:
> Of course there may be other int/long/signed/unsigned sloppynesses
> in there. The warnings used to be lingering reminders but we seem
> to be rid of those warnings

I can fix that!  Adding -Wextra (new name for -W) to C{,XX}FLAGS with
gcc-4.3 yields, among other things, the following:

../../verilog-0.9/vpi/sys_readmem.c:544: warning: comparison between signed and unsigned
../../verilog-0.9/vpi/sys_sdf.c:73: warning: comparison between signed and unsigned
../../verilog-0.9/vpi/lxt_write.c:1032: warning: comparison between signed and unsigned
../../verilog-0.9/vpi/lxt_write.c:1917: warning: comparison between signed and unsigned
../../verilog-0.9/vpi/lxt_write.c:2598: warning: comparison between signed and unsigned
../../verilog-0.9/vpi/lxt2_write.c:1047: warning: comparison between signed and unsigned
../../verilog-0.9/vpi/lxt2_write.c:1090: warning: comparison between signed and unsigned
../../verilog-0.9/vpi/lxt2_write.c:1141: warning: comparison between signed and unsigned
../../verilog-0.9/vpi/lxt2_write.c:1150: warning: comparison between signed and unsigned
../../verilog-0.9/vpi/lxt2_write.c:1226: warning: comparison between signed and unsigned
../../verilog-0.9/vpi/lxt2_write.c:1359: warning: comparison between signed and unsigned
../../verilog-0.9/tgt-vvp/draw_mux.c:74: warning: comparison between signed and unsigned
../../verilog-0.9/tgt-vvp/draw_mux.c:81: warning: comparison between signed and unsigned
../../verilog-0.9/tgt-vvp/draw_mux.c:89: warning: comparison between signed and unsigned
../../verilog-0.9/tgt-vvp/draw_mux.c:93: warning: comparison between signed and unsigned
../../verilog-0.9/tgt-vvp/draw_ufunc.c:139: warning: comparison between signed and unsigned
../../verilog-0.9/tgt-vvp/eval_expr.c:750: warning: comparison of unsigned expression >= 0 is always true
../../verilog-0.9/tgt-vvp/eval_expr.c:766: warning: comparison of unsigned expression >= 0 is always true
../../verilog-0.9/tgt-vvp/eval_expr.c:782: warning: comparison of unsigned expression >= 0 is always true
../../verilog-0.9/tgt-vvp/eval_expr.c:797: warning: comparison of unsigned expression >= 0 is always true
../../verilog-0.9/tgt-vvp/modpath.c:30: warning: comparison between signed and unsigned
../../verilog-0.9/tgt-vvp/vvp_scope.c:415: warning: comparison between signed and unsigned
../../verilog-0.9/tgt-vvp/vvp_scope.c:465: warning: comparison between signed and unsigned
../../verilog-0.9/tgt-vvp/vvp_scope.c:548: warning: comparison between signed and unsigned
../../verilog-0.9/tgt-vvp/vvp_scope.c:567: warning: comparison between signed and unsigned
../../verilog-0.9/tgt-vvp/vvp_scope.c:583: warning: comparison between signed and unsigned
../../verilog-0.9/tgt-vvp/vvp_scope.c:602: warning: comparison between signed and unsigned
../../verilog-0.9/tgt-vvp/vvp_scope.c:1252: warning: comparison between signed and unsigned
../../verilog-0.9/tgt-vvp/vvp_scope.c:1398: warning: comparison between signed and unsigned
../../verilog-0.9/tgt-vvp/vvp_scope.c:1418: warning: comparison between signed and unsigned
../../verilog-0.9/tgt-vvp/vvp_scope.c:1418: warning: comparison between signed and unsigned
../../verilog-0.9/tgt-vvp/vvp_scope.c:1426: warning: comparison between signed and unsigned

I looked at vvp_scope.c; those are a mix of assert()s and for loops.
Maybe innocuous.

   - Larry