Re: [Iverilog-devel] Two people working on pr1879226

[Stephen W. <st...@ic...>]

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So the status of this is that I'm waiting for Larry to integrate
these suggestions and the test program, then he will update the
submitted patch in the Patches tracker?

Cary R. wrote:
> --- Larry Doolittle <ldo...@re...> wrote:
> 
>>> I would also change the comment to be "If
>>> the entire value is shifted away connect the output to a constant V0
>> or
>>> for arithmetic right shift ">>>"  connect all bits to the MSB."
>> OK.  Except that additional detail applies whether or not all
>> of the value is shifted away.  How about putting it in front of the
>> 	if (op_ == 'R') {
>> block?
> 
> Yes the description of what the previous block is doing could go there
> instead. You still need something to say that the new conditional is
> checking for all the bits being shifted. 
> 
>> I'm quite curious to find out if that new assert() in netlist.cc ever
>> gets triggered in the wild.
> 
> The test suite and my local tests pass without any additional failures.
> 
> I'm sending you my modified test code in a separate message that you need
> to include with the final patch so Steve can add it to the test suite. I
> also changed the pr to make you be the "Assigned To:" person. The original
> test code Uwe submitted has some problems that make it not work correctly
> with the test suite and it did not check all the cases ARS can be either 0
> or 1 depending on the MSB.

- --
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
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