[Iverilog-devel] Simulation time in a continuous assignment.

[Cary R. <cy...@ya...>]

Given this piece of code

module top;
  real rtrig = 0.0;
  wire real rval;

  assign rval = rtrig * $realtime;
// assign rval = rtrig * (2.0 * $realtime); // This should also work.

  initial begin
    #1 rtrig = 1.0;
    #1 rtrig = 0.0;
    #1 rtrig = 1.0;
    #1 rtirg = 0.0;
  end
endmodule

I would expect the time value to be evaluated when the rtrig signal
changes. I would expect this to work for an arbitrarily complex equation.
GPL Cver does work this way, so even though nothing in the standard
mentions this specific case it seems reasonable that things should work
this way. The problem is we currently have no way to feedback to the
$realtime function that it should generate a new result.

Any thoughts?

My first thought is to build some kind of triggered .sfunc that can only
be triggered once per time step. The trigger would be any change in the
equation output.

If someone else would like to take this on I can submit a bug report. I'm
a ways off from having time to work on it, but thought I would try to get
some input while it is still fresh in my mind.

Cary


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