Re: [Iverilog-devel] How to get more information when internal errors happen

[Larry D. <ldo...@re...>]

On Fri, Jan 25, 2008 at 10:33:40AM -0800, Stephen Williams wrote:
> Larry Doolittle wrote:
> > This particular bug looks like it's in the vvp code generator.
> > It prints out
> > L_0x81cde48 .concat [ 4 2 0 0], C4<0000>, L_0x81cdef0;
> > but the second width (2) should really be 0. [chop]
> > The elaborated design itself looks correct.
> 
> The elaboration is probably *not* correct if L_0x81cdef0 is
> thought to be width of zero. It looks like the concat writer
> thinks it should be width of 2.

L_0x81cdef0 is thought to be width of zero.
The output from debug:elaborate shows the second concatenate
input has width 0.  The concat output of vvp code generator
is the first place the error appears.

> At this point, the -tstub target may be the needed magic. That
> code generator doubles as a compiler sanity checker and may detect
> the bad situation here. Just run iverilog -v -Wall -tstub test_tb.v
> and see if the resulting a.out has ERROR strings in it anywhere.

That's cool magic.  ;-)

  LPM_CONCAT _s3: <width=4, inputs=2>
    O: test.a_int
    I0: test._s1 (width=4)
    I1: test._s5 (width=2)
    ERROR! Got 6 bits input, expecting 4!
  LPM_PART_VP _s4: <width=0, base=0, signed=0>
    O: test._s5
    I: test.A
    ERROR: Part select input mistatch. Nexus width=2, expect width=0

   - Larry