Re: [Iverilog-devel] How to get more information when internal errors happen

[Uwe B. <bo...@el...>]

>>>>> "Cary" == Cary R <cy...@ya...> writes:

Hallo,

setting 
bool debug_elaborate = true;
in main.cc seems to do the trick:
> iverilog test_tb.v
test_tb.v:2: debug: Create signal reg [3:0] A in scope test
test_tb.v:4: debug: Create signal wire [3:0] a_int in scope test
test_tb.v:6: debug: PGassign: elaborated l-value width=4, type=logic
test_tb.v:6: debug: Elaborate shift (l) as concatenation of 4 zeros with 0 bits of expres

> ./a.out
internal error: port 1 expects wid=2, got wid=0
vvp: concat.cc:56: virtual void vvp_fun_concat::recv_vec4(vvp_net_ptr_t, const vvp_vector4_t&): Assertion `0' failed.
Abort

B.t.w.: can we switch on debug_elaborate on the command line?

Bye
-- 
Uwe Bonnes                bo...@el...

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
module  test();
   reg [3 : 0] A;
   
   wire [3 : 0] a_int;
   
   assign 	a_int = A<<4;
   
endmodule // test