Re: [Iverilog-devel] How to get more information when internal errors happen

[Cary R. <cy...@ya...>]

--- Uwe Bonnes <bo...@el...> wrote:

> I posted the lines driving L_0xc1264c8.

Unless I'm missing something you only showed what L_0xc1264c8 is driving
(input) not what is driving L_0xc1264c8 (output). We also don't know where
L_0xc425280 (the output of the .concat) is going. We know net BU1155_Q is
involved. The Verilog code you showed may be the only places where net
BU1155_Q is used, but it appears the compiler is doing something wrong, so
we cannot make too many assumptions about what is really going on.

I also would have expected the n# nodes to show up some where. Maybe they
did and you didn't include that information.

If you think you have narrowed down the code that is causing the problem
you can print out appropriate information (widths, etc) during elaboration
to see if they match what you expect. If the width is correct at
elaboration, but incorrect in the a.out file it could be a problem in the
code generator or something in the back end of the compiler. If they are
wrong at elaboration then you have to look at the values created at the
initial compile step.

> However I still don't see the code causing the error. But I have the
> feeling
> that it is still caused by a negative parameter upsetting something (see
> iverilog-Bugs-1875866)...

Possibly.

Cary



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