[Iverilog-devel] Inconsistent initial delay value.

[Cary R. <cy...@ya...>]

I am working on checking the bit based delays in continuous assignments
and ran into some inconsistencies between the real test and the bit based
tests. For example:

assign #1 ieq = ia == 1;

is giving a different initial value than:

assign #1 req = ra == 1.0;

ieq appears to be getting the correct result. A .delay statement defaults
to 'bx output, but the real comparison is giving 'bz. Different bit based
delays are defaulting to 'bz. Attached is a simple example. Any clues
about what might be causing the inconsistencies?

Cary


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