[Iverilog-devel] How to get more information when internal errors happen

[Uwe B. <bo...@el...>]

Hallo,

trying to run a XILINX EDK generated Cordic File the first problem met is
the "negative value in for loop" problem, entered in the Bug database
yesterday. I worked around the problem in my local codebase. Trying to run
the generated a.out, I get:
> ./a.out
VCD info: dumpfile iq2phase.vcd opened for output.
internal error: port 1 expects wid=2, got wid=0
vvp: concat.cc:56: virtual void vvp_fun_concat::recv_vec4(vvp_net_ptr_t, \
const vvp_vector4_t&): Assertion `0' failed.
Abort

How can i get more informations in this case to track down the problem?

I asked a similar question last year, where ivl_assert was brought up in the
discussion. However I don't think, ivl_assert may be applied here.

Any hints welcome.
-- 
Uwe Bonnes                bo...@el...

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
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