Re: [Iverilog-devel] Delays in continuous assignment

[Cary R. <cy...@ya...>]

--- Stephen Williams <st...@ic...> wrote:
> I don't think it's an implementation difference so much as a lack
> of implementation in the non-logic cases. It has so non turned up
> in the real works that no one seemed to notice that arithmetic nodes
> don't have delays:-)

And then there is me! It turns out that when you want to do rudimentary
analog modeling adding some delay at the right place can be the difference
between almost working and working correctly. 
 
> At the ivl core (and ivl_target.h) stage, I think all the delays should
> be handled like with the NetLogic devices. In the case of the NetNode
> objects, it may make sense to create a base class to generalize all
> the devices that have a single output that may be delayed (that would
> include the logic gates and the arithmetic gates) as a way to factor
> the delay handling code.

What was confusing me is I had not noticed the NetNode (base class)
pointer was only used when more than one different subclass object was
used in the same routine.

The delay information is actually kept in the NetObj class (parent of
NetNode), so I will look there as a place to generalize the code.

Cary


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