Re: [Iverilog-devel] Delays in continuous assignment

[Stephen W. <st...@ic...>]

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Cary R. wrote:
> It appears that only the bit operators support a delayed continuous
> assignment. I assume that the mathematical, comparison, shift, functions
> and logical operators are expected to have them as well, but they have not
> been fully implemented. I looking in elab_net.cc and it appears that this
> was started for some of these e.g.(elaborate_net_add_). For the bit
> operators the delays were added directly to the object, but for the
> addition/subtraction and the others objects they were added to a NetNode
> object that is then added to the design. Why the difference?

I don't think it's an implementation difference so much as a lack
of implementation in the non-logic cases. It has so non turned up
in the real works that no one seemed to notice that arithmetic nodes
don't have delays:-)

At the vvp level, all delays can (and should) be handled by a delay
node.

At the ivl core (and ivl_target.h) stage, I think all the delays should
be handled like with the NetLogic devices. In the case of the NetNode
objects, it may make sense to create a base class to generalize all
the devices that have a single output that may be delayed (that would
include the logic gates and the arithmetic gates) as a way to factor
the delay handling code.

> So what I'm after is a bit of a road map. I'm willing to work through all
> the tedium to add these and make sure things work correctly (even for real
> values), but some insight would make it much easier. I'm assuming the
> basic path is attach the delays to an object, that object will somehow
> pass this onto an IVL_LPM object. We will need to add an ivl_lpm_delay()
> function to get the delays for the code generator. Modify the code
> generator to create the appropriate .delay functor. Make sure the delay
> functor works correctly with real values.
> 
> Any help would be greatly appreciated!


- --
Steve Williams                "The woods are lovely, dark and deep.
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