From: Cary R. <cy...@ya...> - 2008-01-15 20:09:31
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--- Stephen Williams <st...@ic...> wrote: > My SystemVerilog draft is too old to show this, but I think the > attribute assignment may include a type declaration along with the > assignment. That would mean that in principle the existing attribute > code can be extended in a SV-ish way to make the given code work. > I think *this* is what we want to do. I agree we should code to a standard. If this is supported in SV we need to know what the particulars are. Unfortunately it appears the two people most likely to implement it do not have access to the SV standard (1800-2005). >From memory I don't think the SV standard is too expensive, but it uses the 1364-2005 standard as a base document. I only have a copy of 1364-2001, so I'm probably not going to spend the money to get both standards just to enhance iverilog. Cary ____________________________________________________________________________________ Looking for last minute shopping deals? Find them fast with Yahoo! Search. http://tools.search.yahoo.com/newsearch/category.php?category=shopping |