Re: [Iverilog-devel] Partial fix for pr1867161

[Stephen W. <st...@ic...>]

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Cary R. wrote:
> In the solution to the second problem I am considering changing %load/vp0
> to take the result width not the vector width. The vector does contain
> width information and I'm using that when copying bits to the result. I
> could add another parameter, but then %load/vp0 would have 4 and that will
> require increasing the size of the opcode table.

Actually, I think there was an obscure reason for the way it is
currently. I recall that it's current behavior is used to do some
specialized part selects in place. For example, if a smaller
load width N is given, then only the first N bits are loaded.
This is a common case. It might be that %load/vp0 is not used
that way, but I'm pretty sure that %load/v is.

The opcode.txt file give some guidance here.

- --
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
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iD8DBQFHh5UTrPt1Sc2b3ikRAvJGAJ9PdcycvleqY/aeWoWXxBKw8FXuTgCfY/Bm
yXtYgA+FwYjx9S9Nbj29DBs=
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