From: Cary R. <cy...@ya...> - 2012-08-15 01:58:25
Attachments:
scanf_tests.zip
|
Attached are a few files that test the scanf routines %z functionality in various error/corner cases. Can I please get them tested on a few simulators. For some of them the actual out is important so just include the output for everything to be safe. Some results may be endian dependent, but I'll assume everyone is running on some kind of x86 machine unless I see something weird in the results. I hope this testing will give me enough information to finish implementing the %u and %z opcodes for the Icarus %scanf routines. Thanks in advance, Cary |
From: Iztok J. <izt...@gm...> - 2012-08-15 17:52:52
Attachments:
scanf_tests.log
run_modelsim.sh
|
Hi Cary, This (attached) is from the latest ModelSim Altera edition (free edition). Regards, Iztok Jeras On Wed, Aug 15, 2012 at 3:58 AM, Cary R. <cy...@ya...> wrote: > Attached are a few files that test the scanf routines %z functionality in various error/corner cases. Can I please get them tested on a few simulators. For some of them the actual out is important so just include the output for everything to be safe. Some results may be endian dependent, but I'll assume everyone is running on some kind of x86 machine unless I see something weird in the results. > > I hope this testing will give me enough information to finish implementing the %u and %z opcodes for the Icarus %scanf routines. > > > Thanks in advance, > > Cary > ------------------------------------------------------------------------------ > Live Security Virtual Conference > Exclusive live event will cover all the ways today's security and > threat landscape has changed and how IT managers can respond. Discussions > will include endpoint security, mobile security and the latest in malware > threats. http://www.accelacomm.com/jaw/sfrnl04242012/114/50122263/ > _______________________________________________ > Iverilog-devel mailing list > Ive...@li... > https://lists.sourceforge.net/lists/listinfo/iverilog-devel > |
From: Jared C. <jar...@gm...> - 2012-08-15 18:10:25
|
NCVerilog output: $ for f in scanf_z*.v; do yes "=====" | head -n 5; ncverilog $f; done ===== ===== ===== ===== ===== ncverilog: 06.20-s011: (c) Copyright 1995-2008 Cadence Design Systems, Inc. file: scanf_z_1a.v module worklib.top:v errors: 0, warnings: 0 Caching library 'worklib' ....... Done Elaborating the design hierarchy: Building instance overlay tables: .................... Done Generating native compiled code: worklib.top:v <0x3012fdb6> streams: 1, words: 3157 Loading native compiled code: .................... Done Building instance specific data structures. Design hierarchy summary: Instances Unique Modules: 1 1 Registers: 4 4 Initial blocks: 1 1 Writing initial simulation snapshot: worklib.top:v Loading snapshot worklib.top:v .................... Done ncsim> source /cad/cadence/IUS6.20.lnx86/tools/inca/files/ncsimrc ncsim> run 100z111x_101xxxzz_001z000x_000x100z 00000000_00000000_00000000_00000000 00000000_00000000_00000000_00000000 WARNING: SYSTF FMTNOTA The %Z format does not make sense for $sscanf. ./scanf_z_1a.v, 13: $sscanf(str,"%z",out) FAILED: $sscanf() returned 0 ncsim: *W,RNQUIE: Simulation is complete. ncsim> exit ===== ===== ===== ===== ===== ncverilog: 06.20-s011: (c) Copyright 1995-2008 Cadence Design Systems, Inc. file: scanf_z_1b.v module worklib.top:v errors: 0, warnings: 0 Caching library 'worklib' ....... Done Elaborating the design hierarchy: Building instance overlay tables: .................... Done Generating native compiled code: worklib.top:v <0x011db640> streams: 1, words: 2869 Loading native compiled code: .................... Done Building instance specific data structures. Design hierarchy summary: Instances Unique Modules: 1 1 Registers: 4 4 Initial blocks: 1 1 Writing initial simulation snapshot: worklib.top:v Loading snapshot worklib.top:v .................... Done ncsim> source /cad/cadence/IUS6.20.lnx86/tools/inca/files/ncsimrc ncsim> run 000x100z_001z000x_101xxxzz_100z111x 000x100z_001z000x_101xxxzz_100z111x PASSED ncsim: *W,RNQUIE: Simulation is complete. ncsim> exit ===== ===== ===== ===== ===== ncverilog: 06.20-s011: (c) Copyright 1995-2008 Cadence Design Systems, Inc. file: scanf_z_2.v module worklib.top:v errors: 0, warnings: 0 Caching library 'worklib' ....... Done Elaborating the design hierarchy: Building instance overlay tables: .................... Done Generating native compiled code: worklib.top:v <0x0eb8c5a5> streams: 1, words: 2473 Loading native compiled code: .................... Done Building instance specific data structures. Design hierarchy summary: Instances Unique Modules: 1 1 Registers: 4 4 Initial blocks: 1 1 Writing initial simulation snapshot: worklib.top:v Loading snapshot worklib.top:v .................... Done ncsim> source /cad/cadence/IUS6.20.lnx86/tools/inca/files/ncsimrc ncsim> run 000x100z_001z000x_101xxxzz_100z111x FAILED: $fscanf() returned -1 ncsim: *W,RNQUIE: Simulation is complete. ncsim> exit ===== ===== ===== ===== ===== ncverilog: 06.20-s011: (c) Copyright 1995-2008 Cadence Design Systems, Inc. file: scanf_z_3.v module worklib.top:v errors: 0, warnings: 0 Caching library 'worklib' ....... Done Elaborating the design hierarchy: Building instance overlay tables: .................... Done Generating native compiled code: worklib.top:v <0x011db640> streams: 1, words: 2978 Loading native compiled code: .................... Done Building instance specific data structures. Design hierarchy summary: Instances Unique Modules: 1 1 Registers: 4 4 Initial blocks: 1 1 Writing initial simulation snapshot: worklib.top:v Loading snapshot worklib.top:v .................... Done ncsim> source /cad/cadence/IUS6.20.lnx86/tools/inca/files/ncsimrc ncsim> run 100x100z_001z000x_101xxxzz_100z111x FAILED: 100x100z001z000x101xxxzz100z111x !== 00000000000000000000000000000000100x100z001z000x101xxxzz100z111x ncsim: *W,RNQUIE: Simulation is complete. ncsim> exit ===== ===== ===== ===== ===== ncverilog: 06.20-s011: (c) Copyright 1995-2008 Cadence Design Systems, Inc. file: scanf_z_4.v module worklib.top:v errors: 0, warnings: 0 Caching library 'worklib' ....... Done Elaborating the design hierarchy: Building instance overlay tables: .................... Done Generating native compiled code: worklib.top:v <0x011db640> streams: 1, words: 2978 Loading native compiled code: .................... Done Building instance specific data structures. Design hierarchy summary: Instances Unique Modules: 1 1 Registers: 4 4 Initial blocks: 1 1 Writing initial simulation snapshot: worklib.top:v Loading snapshot worklib.top:v .................... Done ncsim> source /cad/cadence/IUS6.20.lnx86/tools/inca/files/ncsimrc ncsim> run 100x100z_001z000x_101xxxzz_100z111x FAILED: 100x100z001z000x101xxxzz100z111x !== 00000000000000000000000000000000100x100z001z000x101xxxzz100z111x ncsim: *W,RNQUIE: Simulation is complete. ncsim> exit ===== ===== ===== ===== ===== ncverilog: 06.20-s011: (c) Copyright 1995-2008 Cadence Design Systems, Inc. file: scanf_z_5.v module worklib.top:v errors: 0, warnings: 0 Caching library 'worklib' ....... Done Elaborating the design hierarchy: Building instance overlay tables: .................... Done Generating native compiled code: worklib.top:v <0x17a30a6d> streams: 1, words: 4676 Loading native compiled code: .................... Done Building instance specific data structures. Design hierarchy summary: Instances Unique Modules: 1 1 Registers: 5 5 Initial blocks: 1 1 Writing initial simulation snapshot: worklib.top:v Loading snapshot worklib.top:v .................... Done ncsim> source /cad/cadence/IUS6.20.lnx86/tools/inca/files/ncsimrc ncsim> run 000x100z_001z000x_101xxxzz_100z111x 000x100z_001z000x_101xxxzz_100z111x 100x100z_001z000x_101xxxzz_100z111x 100x100z_001z000x_101xxxzz_100z111x PASSED ncsim: *W,RNQUIE: Simulation is complete. ncsim> exit ===== ===== ===== ===== ===== ncverilog: 06.20-s011: (c) Copyright 1995-2008 Cadence Design Systems, Inc. file: scanf_z_6.v module worklib.top:v errors: 0, warnings: 0 Caching library 'worklib' ....... Done Elaborating the design hierarchy: Building instance overlay tables: .................... Done Generating native compiled code: worklib.top:v <0x323ec9e7> streams: 1, words: 2268 Loading native compiled code: .................... Done Building instance specific data structures. Design hierarchy summary: Instances Unique Modules: 1 1 Registers: 4 4 Initial blocks: 1 1 Writing initial simulation snapshot: worklib.top:v Loading snapshot worklib.top:v .................... Done ncsim> source /cad/cadence/IUS6.20.lnx86/tools/inca/files/ncsimrc ncsim> run 101xxxzz_100z111x 101xxxzz_100z111x PASSED ncsim: *W,RNQUIE: Simulation is complete. ncsim> exit ===== ===== ===== ===== ===== ncverilog: 06.20-s011: (c) Copyright 1995-2008 Cadence Design Systems, Inc. file: scanf_z_7.v module worklib.top:v errors: 0, warnings: 0 Caching library 'worklib' ....... Done Elaborating the design hierarchy: Building instance overlay tables: .................... Done Generating native compiled code: worklib.top:v <0x323ec9e7> streams: 1, words: 2349 Loading native compiled code: .................... Done Building instance specific data structures. Design hierarchy summary: Instances Unique Modules: 1 1 Registers: 4 4 Initial blocks: 1 1 Writing initial simulation snapshot: worklib.top:v Loading snapshot worklib.top:v .................... Done ncsim> source /cad/cadence/IUS6.20.lnx86/tools/inca/files/ncsimrc ncsim> run 000x100z_001z000x_101xxxzz_100z111x 000x100z_001z000x_101xxxzz_100z111x ncsim: *W,RNQUIE: Simulation is complete. ncsim> exit On Tue, Aug 14, 2012 at 6:58 PM, Cary R. <cy...@ya...> wrote: > Attached are a few files that test the scanf routines %z functionality in various error/corner cases. Can I please get them tested on a few simulators. For some of them the actual out is important so just include the output for everything to be safe. Some results may be endian dependent, but I'll assume everyone is running on some kind of x86 machine unless I see something weird in the results. > > I hope this testing will give me enough information to finish implementing the %u and %z opcodes for the Icarus %scanf routines. > > > Thanks in advance, > > Cary > ------------------------------------------------------------------------------ > Live Security Virtual Conference > Exclusive live event will cover all the ways today's security and > threat landscape has changed and how IT managers can respond. Discussions > will include endpoint security, mobile security and the latest in malware > threats. http://www.accelacomm.com/jaw/sfrnl04242012/114/50122263/ > _______________________________________________ > Iverilog-devel mailing list > Ive...@li... > https://lists.sourceforge.net/lists/listinfo/iverilog-devel > |
From: Cary R. <cy...@ya...> - 2012-08-16 01:58:22
|
Here are some comments on the test results, what I think should be done and other questions. NC doesn't support %z and I will assume %u when reading from a string. MSim produces incorrect results. The standard states that $fscanf() is preferred and embedded null bytes will cause problems which is why I made sure there was a z or x and a x or 1 in every byte. Icarus reports when embedded NULL bytes are created in a string so that should be enough to know that the string has problems if you want to read it with $sscanf(). For now I'm going to let $sscanf() get the same code as $fscanf(). The good thing is both the simulators get the base case correct (data written to a file using %z can be read using %z). Test 2 was testing to see what happens when reading with %z and there is not enough data bytes. Both simulators fail and I probably need to create some more test code to probe the subtleties of this. Specifically NC returns EOF since EOF was reached before the %z was fully matched. The problem is %z consumes eight bytes and are the bytes read returned to the stream? I would assume they are not. MSim returns 0 because I assume it noticed that some bytes were available, but not enough to satisfy a single %z structure. Are there any thoughts on if this should be EOF or just 0 (the match failed). I personally like EOF and discarding the bytes. Test 3 looks at what happens if you try to read more words than are in the file. MSim considers this a failure. The one relevant piece of the standard is "The application shall transfer the 4 value binary representation of the specified data from the input stream to the destination register." This does not explicitly say that there must be enough data words to fill the register, but it looks like that is what MSim requires. NC reads the words and then zero fills the rest of the register. Maybe I'm wrong, but my first thought would be that it should sign extend a signed register. I expect test 3 would pass with NC if the registers were not signed. Since we are talking about binary data maybe failure when there are not enough bytes is appropriate. Test 4 is similar to test 3 except it is using a maximum width of 32 to signify that only 32 bits of 4 value data is in the file. MSim ignores the maximum size and because there are not enough bytes is failing. NC is not sign extending like in test 3. More about my thoughts on maximum widths after the individual test discussion. Test 5 writes 64 bits of data and then reads it back in two 32 bit chunks. NC matches what I thought should happen, but MSim has the words reversed so it looks to be writing the words in a different order. I'm guessing MSim has a bug, but I need to double check this. Test 6 writes 32 bits of data but only reads back 16 bits. NC matches what I expect. MSim has a failure, but it looks like the data is being read correctly so I'm not sure this is a $fscanf() with %z error. Note that the error message in missing a slice on the input variable that is in the equality comparison. Test 7 writes 32 bits and specifies that 16 bits should be read back into a 32 bit register. MSim reports it is ignoring the maximum width. NC reads all 32 bits with out a warning. I need to create a test to see if NC really looks at the maximum width or not (e.g. if I write 64 bits of data can I read only 32 bits in to a 64 bit register? My though on this is that it needs to be modulo 32 Verilog bits with rounding (module 64 bits in the file) since that is how it is written. That implies a width of 1 to 32 reads a 32 bit aval and a 32 bit bval word from the file that is then copied to the register as appropriate. This functionality would allow us to correctly skip a 16 bit variable that was saved using %z with the obvious %*16z format sequence (this would really skip 64 bits in the file). I'll try to work on more test code to explore this further, but thoughts on sign extending is appreciated. Cary |
From: Iztok J. <izt...@gm...> - 2012-08-16 16:02:04
Attachments:
run_ncsim.log
run_ncsim.sh
|
Hi Cary, Attached is a the simulation log generated with a more recent version of ncsim (probably July 2012). There probably are a few differences compared to version 6.2 Regards, Iztok Jeras On Thu, Aug 16, 2012 at 3:58 AM, Cary R. <cy...@ya...> wrote: > Here are some comments on the test results, what I think should be done and other questions. > > NC doesn't support %z and I will assume %u when reading from a string. MSim produces incorrect results. The standard states that $fscanf() is preferred and embedded null bytes will cause problems which is why I made sure there was a z or x and a x or 1 in every byte. Icarus reports when embedded NULL bytes are created in a string so that should be enough to know that the string has problems if you want to read it with $sscanf(). For now I'm going to let $sscanf() get the same code as $fscanf(). > > The good thing is both the simulators get the base case correct (data written to a file using %z can be read using %z). > > Test 2 was testing to see what happens when reading with %z and there is not enough data bytes. Both simulators fail and I probably need to create some more test code to probe the subtleties of this. Specifically NC returns EOF since EOF was reached before the %z was fully matched. The problem is %z consumes eight bytes and are the bytes read returned to the stream? I would assume they are not. MSim returns 0 because I assume it noticed that some bytes were available, but not enough to satisfy a single %z structure. Are there any thoughts on if this should be EOF or just 0 (the match failed). I personally like EOF and discarding the bytes. > > Test 3 looks at what happens if you try to read more words than are in the file. MSim considers this a failure. The one relevant piece of the standard is "The application shall transfer the 4 value binary representation of the specified data from the input stream to the destination register." This does not explicitly say that there must be enough data words to fill the register, but it looks like that is what MSim requires. NC reads the words and then zero fills the rest of the register. Maybe I'm wrong, but my first thought would be that it should sign extend a signed register. I expect test 3 would pass with NC if the registers were not signed. Since we are talking about binary data maybe failure when there are not enough bytes is appropriate. > > Test 4 is similar to test 3 except it is using a maximum width of 32 to signify that only 32 bits of 4 value data is in the file. MSim ignores the maximum size and because there are not enough bytes is failing. NC is not sign extending like in test 3. More about my thoughts on maximum widths after the individual test discussion. > > Test 5 writes 64 bits of data and then reads it back in two 32 bit chunks. NC matches what I thought should happen, but MSim has the words reversed so it looks to be writing the words in a different order. I'm guessing MSim has a bug, but I need to double check this. > > Test 6 writes 32 bits of data but only reads back 16 bits. NC matches what I expect. MSim has a failure, but it looks like the data is being read correctly so I'm not sure this is a $fscanf() with %z error. Note that the error message in missing a slice on the input variable that is in the equality comparison. > > Test 7 writes 32 bits and specifies that 16 bits should be read back into a 32 bit register. MSim reports it is ignoring the maximum width. NC reads all 32 bits with out a warning. > > I need to create a test to see if NC really looks at the maximum width or not (e.g. if I write 64 bits of data can I read only 32 bits in to a 64 bit register? My though on this is that it needs to be modulo 32 Verilog bits with rounding (module 64 bits in the file) since that is how it is written. That implies a width of 1 to 32 reads a 32 bit aval and a 32 bit bval word from the file that is then copied to the register as appropriate. This functionality would allow us to correctly skip a 16 bit variable that was saved using %z with the obvious %*16z format sequence (this would really skip 64 bits in the file). > > I'll try to work on more test code to explore this further, but thoughts on sign extending is appreciated. > > Cary > > > ------------------------------------------------------------------------------ > Live Security Virtual Conference > Exclusive live event will cover all the ways today's security and > threat landscape has changed and how IT managers can respond. Discussions > will include endpoint security, mobile security and the latest in malware > threats. http://www.accelacomm.com/jaw/sfrnl04242012/114/50122263/ > _______________________________________________ > Iverilog-devel mailing list > Ive...@li... > https://lists.sourceforge.net/lists/listinfo/iverilog-devel |