iverilog-devel

[Iverilog-devel] Icarus Verilog with Xilinx ISE 10.1

[J. P. B. <jpb...@gm...>]

Hello,
   Please forgive me if I should post this question in a -users list.
   I'm using Xilinx's 10.1 ISE for FPGA design, and I would like to
use Icarus Verilog for simulating my designs.  Is there any way to use
iverilog for simulation with the ISE?  In particular, how can I
utilize Xilinx IP in my iverilog simulations?
   Thanks for your help!

   Patrick

Re: [Iverilog-devel] Icarus Verilog with Xilinx ISE 10.1

[Martin W. <mai...@ma...>]

J. Patrick Bedell wrote:
> Hello,
>    Please forgive me if I should post this question in a -users list.
>    I'm using Xilinx's 10.1 ISE for FPGA design, and I would like to
> use Icarus Verilog for simulating my designs.  Is there any way to use
> iverilog for simulation with the ISE?  In particular, how can I
> utilize Xilinx IP in my iverilog simulations?
>    Thanks for your help!

If you want to simulate RTL code that instantiates Xilinx primitives, then

   iverilog -y ${XILINX}/verilog/src/unisims \
     ${XILINX}/verilog/src/glbl.v your_files...

where ${XILINX} is the path to your Xilinx software installation and 
your_files... is a list of your Verilog source files. If you are using 
Xilinx IP blocks other than primitives, you'll need to find or generate 
Verilog simulation models for these blocks and add them to the list on 
the command line (have a look in ${XILINX}/verilog/src/XilinxCoreLib)

If you want to simulate a placed/routed netlist, you need to generate a 
Verilog netlist from the Xilinx database (use the netgen utility) then

   iverilog -y ${XILINX}/verilog/src/simprims \
     ${XILINX}/verilog/src/glbl.v netlist.v testbench.v

where netlist.v is the Verilog nelist produced by netgen and testbench.v 
is your test framework for exercising the device.

The above assumes you are running some flavour of Unix. If you are using 
Windows, you'll need to adjust the filepath syntax.

Martin

Re: [Iverilog-devel] Icarus Verilog with Xilinx ISE 10.1

[Chitlesh G. <chi...@gm...>]

On Fri, May 15, 2009 at 1:12 AM, Martin Whitaker  wrote:
> If you want to simulate a placed/routed netlist, you need to generate a
> Verilog netlist from the Xilinx database (use the netgen utility) then
>
>   iverilog -y ${XILINX}/verilog/src/simprims \
>     ${XILINX}/verilog/src/glbl.v netlist.v testbench.v
>
> where netlist.v is the Verilog nelist produced by netgen and testbench.v
> is your test framework for exercising the device.


Hello,

I was never successful in simulating the post placed/route netlist.
This is my command

	iverilog -Wall -g 2x -y . -Tmax -gspecify -gxtypes\
		 -y $(XILINXCADROOT)/verilog/src/simprims \
		 $(PROJECT)_map.v $(PROJECT)_tb.v -o $(PROJECT).exe
	vvp $(PROJECT).exe -gxtypes -sdf-verbose -y
$(XILINXCADROOT)/verilog/src/simprims

These are the errors I get,
freqdiv_tb.v:1: warning: timescale for freqdiv_tb inherited from
another file.
freqdiv_map.v:164: ...: The inherited timescale is here.
vvp freqdiv.exe -gxtypes -sdf-verbose -y
/opt/xilinx/ISE/10.1.03_K.39/ISE/verilog/src/simprims
freqdiv_map.sdf:3:SDF INFO: Design: freqdiv
freqdiv_map.sdf:4:SDF INFO: Date: Wed May 13 13:25:11 2009
freqdiv_map.sdf:5:SDF INFO: Vendor: Xilinx
freqdiv_map.sdf:6:SDF INFO: Program: Xilinx SDF Writer
freqdiv_map.sdf:7:SDF INFO: Program Version: K.39
freqdiv_map.sdf:11:SDF INFO: TIMESCALE : 1.000000ps
SDF WARNING: freqdiv_map.v:57: Unable to match ModPath I -> O in
freqdiv_tb.UT.o_Out_OBUF
freqdiv_map.sdf:SDF ERROR: Too many errors: syntax error
freqdiv_map.sdf:21:SDF ERROR: Invalid/malformed INSTANCE argument
SDF WARNING: freqdiv_map.v:57: Module  in freqdiv_tb.UT is not a
X_BUF; it is an freqdiv_tb.UT
SDF WARNING: freqdiv_map.v:57: Unable to match ModPath I -> O in freqdiv_tb.UT
freqdiv_map.sdf:SDF ERROR: Too many errors: syntax error
freqdiv_map.sdf:29:SDF ERROR: Invalid/malformed INSTANCE argument
SDF WARNING: freqdiv_map.v:57: Module  in freqdiv_tb.UT is not a
X_BUF; it is an freqdiv_tb.UT
SDF WARNING: freqdiv_map.v:57: Unable to match ModPath I -> O in freqdiv_tb.UT
vvp: delay.cc:714: void modpath_src_put_delays(__vpiHandle*,
t_vpi_delay*): Assertion `0' failed.
make: *** [poststa] Aborted

Can you shed some light on which magic trick you use ?

regards,
Chitlesh

Re: [Iverilog-devel] Icarus Verilog with Xilinx ISE 10.1

[Larry D. <ldo...@re...>]

Martin -

On Fri, May 15, 2009 at 12:12:56AM +0100, Martin Whitaker wrote:
> If you want to simulate RTL code that instantiates Xilinx primitives, then
> 
>    iverilog -y ${XILINX}/verilog/src/unisims \
>      ${XILINX}/verilog/src/glbl.v your_files...
> 
> where ${XILINX} is the path to your Xilinx software installation and 
> your_files... is a list of your Verilog source files.

The downside of that approach is that only people with (non-free)
Xilinx software installed can simulate your code.  I tend to write
stripped-down free replacments for each primitive I use.

I have versions of
 FDDRRSE.v
 BUFG.v
 IBUF.v
 SRL16E.v
and, leftover from the days when XST wasn't very good about
synthesizing dual-port RAM,
 RAMB16_S18_S18.v
 RAMB4_S16_S16.v
 RAMB4_S8_S8.v
 RAMB16_S2_S2.v
 RAMB4_S4_S4.v
They're pretty short, and don't take very long to write.
I always put a (* ivl_synthesis_cell *) in each to prepare for
the day when Icarus will have a useful synthesis capability.

   - Larry