iverilog-devel

[Iverilog-devel] The string type and $value$plusargs

[<ni...@ly...>]

I'm now trying to read a memory dump, using a command line argument for
the file name (as hinted at the end of
http://iverilog.wikia.com/wiki/Simulation).

System verilog has a string type, so I tried this program,

  module main;
     reg [64:0] mem [0:100];
     string img;
     initial begin
        if (!$value$plusargs("img=%s", img)) begin
           $display("Specify image file with +img=<image>.");
           $finish_and_return(1);
        end
        $display("Using image: %s", img);
        $readmemh(img, mem);      
        $display("Initial memory word: mem[0] = %x", mem[0]);
        $finish;
     end
  endmodule // main

I compile using

  $ iverilog -g2005-sv main.vl -o main

(with iverilog compiled from git eariler today). Works fine, so far. But
running it fails,

  $ ./main +img=../examples/hello.hex
  ERROR: main.vl:5: $value$plusargs's second argument must be a variable, found a vpiStringVar.

If I change "string img;" to "reg [300:0] img;" it works, and I get the output

  Using image:                  ../examples/hello.hex
  WARNING: main.vl:10: $readmemh(../examples/hello.hex): Not enough words in the file for the requested range [0:100].
  Initial memory word: mem[0] = 07000b4a08408e500

But that doesn't seem like a very good solution, since I have to put an
arbitrary size on the register, and it will fail with filenames which
exceed this size.

If I try the System verilog support in iverilog (primarily, I would like
to use the interface abstraction), I should be able to use the vlog95
target to generate plain verilog code which I could feed to, e.g.,
yosys, right?

Regards,
/Niels

-- 
Niels Möller. PGP-encrypted email is preferred. Keyid C0B98E26.
Internet email is subject to wholesale government surveillance.

[Iverilog-devel] System Verilog and interfaces

[<ni...@ly...>]

Speaking of System Verilog and interfaces, what's the current status of
System Verilog support?

Consider the first example on
http://www.doulos.com/knowhow/sysverilog/tutorial/interfaces/, which
could be cut down a bit to the following:

  // Interface definition
  interface Bus;
    logic [7:0] Addr, Data;
    logic RWn;
  endinterface
  
  module RAM (Bus MemBus); /* ! */
  endmodule

This gives a syntax error on the line marked /* ! */,

  $ iverilog -g2005-sv interface.vl
  interface.vl:7: syntax error
  interface.vl:7: Errors in port declarations.

I had a quick look in the source code, and I see nothing in parse.y to
allow a named interface as a data type. I'm a bit in the dark as to how
these things work. Maybe pform.cc:pform_test_type_identifier should look
up known interfaces? In the grammar for the non-terminal
port_declaration, it looks like a named interface, which I guess is just
an IDENTIFIER to the lexer, ought to be parsed as part of the
data_type_or_implicit non-terminal.

Currently, it seems defining an interface (at top-level) adds the
interface to pform_modules, as an instance of Module with is_interface
== true. While defining other types (typedef, struct, or class) adds an
entry to pform_typedefs.

Regards,
/Niels

-- 
Niels Möller. PGP-encrypted email is preferred. Keyid C0B98E26.
Internet email is subject to wholesale government surveillance.

Re: [Iverilog-devel] System Verilog and interfaces

[Martin W. <mai...@ma...>]

I'm working on adding support for interfaces as and when I have free time. As 
you have found, at present you can define and instantiate an interface, but 
nothing more.

ni...@ly... (Niels Möller) wrote:
> Speaking of System Verilog and interfaces, what's the current status of
> System Verilog support?
>
> Consider the first example on
> http://www.doulos.com/knowhow/sysverilog/tutorial/interfaces/, which
> could be cut down a bit to the following:
>
>    // Interface definition
>    interface Bus;
>      logic [7:0] Addr, Data;
>      logic RWn;
>    endinterface
>
>    module RAM (Bus MemBus); /* ! */
>    endmodule
>
> This gives a syntax error on the line marked /* ! */,
>
>    $ iverilog -g2005-sv interface.vl
>    interface.vl:7: syntax error
>    interface.vl:7: Errors in port declarations.
>
> I had a quick look in the source code, and I see nothing in parse.y to
> allow a named interface as a data type. I'm a bit in the dark as to how
> these things work. Maybe pform.cc:pform_test_type_identifier should look
> up known interfaces? In the grammar for the non-terminal
> port_declaration, it looks like a named interface, which I guess is just
> an IDENTIFIER to the lexer, ought to be parsed as part of the
> data_type_or_implicit non-terminal.
>
> Currently, it seems defining an interface (at top-level) adds the
> interface to pform_modules, as an instance of Module with is_interface
> == true. While defining other types (typedef, struct, or class) adds an
> entry to pform_typedefs.
>
> Regards,
> /Niels
>

Re: [Iverilog-devel] System Verilog and interfaces

[<ni...@ly...>]

Martin Whitaker <mai...@ma...> writes:

> I'm working on adding support for interfaces as and when I have free
> time.

I really appreciate that. And I take it the progress will be reported on
this list.

Thanks,
/Niels

-- 
Niels Möller. PGP-encrypted email is preferred. Keyid C0B98E26.
Internet email is subject to wholesale government surveillance.

Re: [Iverilog-devel] The string type and $value$plusargs

[Cary R. <cy...@ya...>]

Hi Niels,
Yes this should work. The problem is the plusargs code was not updated to know that a SystemVerilog string is a variable. Once that was done there is still a problem in that the string is not being updated correctly. I will look at why that is next and post again when I have this working correctly.

Interfaces are not currently supported in Icarus. Once they are I hope that the vlog95 code generator can be enhanced to emit them as normal Verilog. I think it will work, but the internal representation may put constraints on how well that will work.
Cary
 

     On Tuesday, February 10, 2015 6:35 AM, Niels Möller <ni...@ly...> wrote:
   

 I'm now trying to read a memory dump, using a command line argument for
the file name (as hinted at the end of
http://iverilog.wikia.com/wiki/Simulation).

System verilog has a string type, so I tried this program,

  module main;
    reg [64:0] mem [0:100];
    string img;
    initial begin
        if (!$value$plusargs("img=%s", img)) begin
          $display("Specify image file with +img=<image>.");
          $finish_and_return(1);
        end
        $display("Using image: %s", img);
        $readmemh(img, mem);      
        $display("Initial memory word: mem[0] = %x", mem[0]);
        $finish;
    end
  endmodule // main

I compile using

  $ iverilog -g2005-sv main.vl -o main

(with iverilog compiled from git eariler today). Works fine, so far. But
running it fails,

  $ ./main +img=../examples/hello.hex
  ERROR: main.vl:5: $value$plusargs's second argument must be a variable, found a vpiStringVar.

If I change "string img;" to "reg [300:0] img;" it works, and I get the output

  Using image:                  ../examples/hello.hex
  WARNING: main.vl:10: $readmemh(../examples/hello.hex): Not enough words in the file for the requested range [0:100].
  Initial memory word: mem[0] = 07000b4a08408e500

But that doesn't seem like a very good solution, since I have to put an
arbitrary size on the register, and it will fail with filenames which
exceed this size.

If I try the System verilog support in iverilog (primarily, I would like
to use the interface abstraction), I should be able to use the vlog95
target to generate plain verilog code which I could feed to, e.g.,
yosys, right?

Regards,
/Niels

-- 
Niels Möller. PGP-encrypted email is preferred. Keyid C0B98E26.
Internet email is subject to wholesale government surveillance.


------------------------------------------------------------------------------
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hub for all things parallel software development, from weekly thought
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look and join the conversation now. http://goparallel.sourceforge.net/
_______________________________________________
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Re: [Iverilog-devel] The string type and $value$plusargs

[Cary R. <cy...@ya...>]

I have pushed a patch that fixes the oversight in updating the plusargs routine to allow SV strings and add support to put a string value to a SV string from the VPI. If you get the latest code from git this should now work correctly.
Cary
 

     On Wednesday, February 25, 2015 6:12 PM, Cary R. <cy...@ya...> wrote:
   

 Hi Niels,
Yes this should work. The problem is the plusargs code was not updated to know that a SystemVerilog string is a variable. Once that was done there is still a problem in that the string is not being updated correctly. I will look at why that is next and post again when I have this working correctly.

Interfaces are not currently supported in Icarus. Once they are I hope that the vlog95 code generator can be enhanced to emit them as normal Verilog. I think it will work, but the internal representation may put constraints on how well that will work.
Cary
 

     On Tuesday, February 10, 2015 6:35 AM, Niels Möller <ni...@ly...> wrote:
   

 I'm now trying to read a memory dump, using a command line argument for
the file name (as hinted at the end of
http://iverilog.wikia.com/wiki/Simulation).

System verilog has a string type, so I tried this program,

  module main;
    reg [64:0] mem [0:100];
    string img;
    initial begin
        if (!$value$plusargs("img=%s", img)) begin
          $display("Specify image file with +img=<image>.");
          $finish_and_return(1);
        end
        $display("Using image: %s", img);
        $readmemh(img, mem);      
        $display("Initial memory word: mem[0] = %x", mem[0]);
        $finish;
    end
  endmodule // main

I compile using

  $ iverilog -g2005-sv main.vl -o main

(with iverilog compiled from git eariler today). Works fine, so far. But
running it fails,

  $ ./main +img=../examples/hello.hex
  ERROR: main.vl:5: $value$plusargs's second argument must be a variable, found a vpiStringVar.

If I change "string img;" to "reg [300:0] img;" it works, and I get the output

  Using image:                  ../examples/hello.hex
  WARNING: main.vl:10: $readmemh(../examples/hello.hex): Not enough words in the file for the requested range [0:100].
  Initial memory word: mem[0] = 07000b4a08408e500

But that doesn't seem like a very good solution, since I have to put an
arbitrary size on the register, and it will fail with filenames which
exceed this size.

If I try the System verilog support in iverilog (primarily, I would like
to use the interface abstraction), I should be able to use the vlog95
target to generate plain verilog code which I could feed to, e.g.,
yosys, right?

Regards,
/Niels

-- 
Niels Möller. PGP-encrypted email is preferred. Keyid C0B98E26.
Internet email is subject to wholesale government surveillance.


------------------------------------------------------------------------------
Dive into the World of Parallel Programming. The Go Parallel Website,
sponsored by Intel and developed in partnership with Slashdot Media, is your
hub for all things parallel software development, from weekly thought
leadership blogs to news, videos, case studies, tutorials and more. Take a
look and join the conversation now. http://goparallel.sourceforge.net/
_______________________________________________
Iverilog-devel mailing list
Ive...@li...
https://lists.sourceforge.net/lists/listinfo/iverilog-devel

    

   

Re: [Iverilog-devel] The string type and $value$plusargs

[<ni...@ly...>]

"Cary R." <cy...@ya...> writes:

> I have pushed a patch that fixes the oversight in updating the
> plusargs routine to allow SV strings and add support to put a string
> value to a SV string from the VPI. If you get the latest code from git
> this should now work correctly.

I've tested it now, and I can confirm that it works fine. To recap, the
usecase was

   string img;
   if (!$value$plusargs("img=%s", img)) begin
      $display("Specify image file with +img=<image>.");
      $finish_and_return(1);
   end
   $readmemh(img, main_storage.mem);

Thanks!
/Niels

-- 
Niels Möller. PGP-encrypted email is preferred. Keyid C0B98E26.
Internet email is subject to wholesale government surveillance.