iverilog-devel

[Iverilog-devel] Fopen the same file twice for writeing?

[Andrei P. <pur...@gm...>]

Hello!
I have found a weird modelsim behavior where if you open the same
filename twice with the one-parameter (multichannel descriptor) $fopen
then one of the fopens will not overwrite the other one, but instead
both outputs end up in the output file.

Iverilog behaves the way i'd expect it to.

Do other simulators behave like modelsim?

(result of the attached .v file)
iverilog:(all versions)

andrew@charon:~$ cat test.txt; rm test.txt
second
second after first is closed
andrew@charon:~$ cat test.txtb; rm test.txtb
second
second after first is closed
andrew@charon:~$ cat test.txtc; rm test.txtc
first


modelsim:

andrew@charon:~$ cat test.txt; rm test.txt
first
second
andrew@charon:~$ cat test.txtb; rm test.txtb
second
second after first is closed
andrew@charon:~$ cat test.txtc; rm test.txtc
first
second

Re: [Iverilog-devel] Fopen the same file twice for writeing?

[Michael S. <mic...@gm...>]

Your test is very wrong. Why do you open the same file in different "always"
blocks?

ncverilog:

ncsim: *W,VFOPTW: File test.txt being opened by Initial stmt (file:
./test.v, line: 8 in worklib.tt [module]) has been opened earlier.
ncsim: *W,VFOPTW: File test.txtb being opened by Initial stmt (file:
./test.v, line: 22 in worklib.tt [module]) has been opened earlier.
ncsim: *W,VFOPTW: File test.txtc being opened by Initial stmt (file:
./test.v, line: 34 in worklib.tt [module]) has been opened earlier.

> cat test.txt; rm test.txt
second
second after first is closed

> cat test.txtb; rm test.txtb
second
second after first is closed

> cat test.txtc; rm test.txtc
first

vcs :
> cat test.txt; rm test.txt
second
second after first is closed

> cat test.txtb; rm test.txtb
second
second after first is closed

> cat test.txtc; rm test.txtc
first



2009/5/27 Andrei Purdea <pur...@gm...>

> Hello!
> I have found a weird modelsim behavior where if you open the same
> filename twice with the one-parameter (multichannel descriptor) $fopen
> then one of the fopens will not overwrite the other one, but instead
> both outputs end up in the output file.
>
> Iverilog behaves the way i'd expect it to.
>
> Do other simulators behave like modelsim?
>
> (result of the attached .v file)
> iverilog:(all versions)
>
> andrew@charon:~$ cat test.txt; rm test.txt
> second
> second after first is closed
> andrew@charon:~$ cat test.txtb; rm test.txtb
> second
> second after first is closed
> andrew@charon:~$ cat test.txtc; rm test.txtc
> first
>
>
> modelsim:
>
> andrew@charon:~$ cat test.txt; rm test.txt
> first
> second
> andrew@charon:~$ cat test.txtb; rm test.txtb
> second
> second after first is closed
> andrew@charon:~$ cat test.txtc; rm test.txtc
> first
> second
>
>
> ------------------------------------------------------------------------------
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>

Re: [Iverilog-devel] Fopen the same file twice for writeing?

[Stephen W. <st...@ic...>]

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1


The behavior you get will depend on the scheduling order of the
initial statements, and to a lesser degree on the operating system.
Icarus Verilog uses fopen(<P>,"w") to open MCD files, and in your
case, opening twice, the second open will truncate the first.

It appears that VCS and ncsim agree with Icarus Verilog, at least
in the broader sense. Modelsim seems to be making some special effort
to detect that you opened the file twice and combine file descriptors,
which may make a small bit of sense given that mcd descriptors are
precious. But really, that strikes me as a lot of effort to support
a bad input.

I think this situation is (and should be) left unspecified. Just
don't do that!-)

Andrei Purdea wrote:
> Hello!
> I have found a weird modelsim behavior where if you open the same
> filename twice with the one-parameter (multichannel descriptor) $fopen
> then one of the fopens will not overwrite the other one, but instead
> both outputs end up in the output file.
> 
> Iverilog behaves the way i'd expect it to.
> 
> Do other simulators behave like modelsim?
> 
> (result of the attached .v file)
> iverilog:(all versions)
> 
> andrew@charon:~$ cat test.txt; rm test.txt
> second
> second after first is closed
> andrew@charon:~$ cat test.txtb; rm test.txtb
> second
> second after first is closed
> andrew@charon:~$ cat test.txtc; rm test.txtc
> first
> 
> 
> modelsim:
> 
> andrew@charon:~$ cat test.txt; rm test.txt
> first
> second
> andrew@charon:~$ cat test.txtb; rm test.txtb
> second
> second after first is closed
> andrew@charon:~$ cat test.txtc; rm test.txtc
> first
> second


- --
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.4-svn0 (GNU/Linux)
Comment: Using GnuPG with SUSE - http://enigmail.mozdev.org

iD8DBQFKHYG7rPt1Sc2b3ikRAiZ1AKCdlj0Yt9QN4eqOX260OlFj6AXCXwCdE4NZ
12LcylRNdAgfXFfhx7EHayk=
=vGwY
-----END PGP SIGNATURE-----

Re: [Iverilog-devel] Fopen the same file twice for writeing?

[Andrei P. <pur...@gm...>]

What i was looking for was Verilog code that could write to the same
file from multiple modules. A piece of code that I found used this
modelsim "feature". Indeed this seems like a strange behaviour to me.
The only solution I can think of for this is distributing the
resulting mcd or simple fd trough ports (which is something i might
not want if I have a structural, maybe synthesizable block, with some
simulation-only children wanting to write the same file), or by the
top level assigning hierarhically the variables in the leaf nodes that
hold the file descriptors. Something that could be painful for example
in the case of generate statements.

I would like to propose an extention for icarus to support a C
freopen-like functionality to redirect stdout. What do you think about
something like this?

Andrew

On Wed, May 27, 2009 at 9:08 PM, Stephen Williams <st...@ic...> wrote:
> The behavior you get will depend on the scheduling order of the
> initial statements, and to a lesser degree on the operating system.
> Icarus Verilog uses fopen(<P>,"w") to open MCD files, and in your
> case, opening twice, the second open will truncate the first.
>
> It appears that VCS and ncsim agree with Icarus Verilog, at least
> in the broader sense. Modelsim seems to be making some special effort
> to detect that you opened the file twice and combine file descriptors,
> which may make a small bit of sense given that mcd descriptors are
> precious. But really, that strikes me as a lot of effort to support
> a bad input.
>
> I think this situation is (and should be) left unspecified. Just
> don't do that!-)

Re: [Iverilog-devel] Fopen the same file twice for writeing?

[Michael S. <mic...@gm...>]

Why don't you open a file in your testbench and then use that variable in
all your modules? In this case you open it once only.

On Sun, May 31, 2009 at 8:46 AM, Andrei Purdea <pur...@gm...>wrote:

> What i was looking for was Verilog code that could write to the same
> file from multiple modules. A piece of code that I found used this
> modelsim "feature". Indeed this seems like a strange behaviour to me.
> The only solution I can think of for this is distributing the
> resulting mcd or simple fd trough ports (which is something i might
> not want if I have a structural, maybe synthesizable block, with some
> simulation-only children wanting to write the same file), or by the
> top level assigning hierarhically the variables in the leaf nodes that
> hold the file descriptors. Something that could be painful for example
> in the case of generate statements.
>
> I would like to propose an extention for icarus to support a C
> freopen-like functionality to redirect stdout. What do you think about
> something like this?
>
> Andrew
>
> On Wed, May 27, 2009 at 9:08 PM, Stephen Williams <st...@ic...>
> wrote:
> > The behavior you get will depend on the scheduling order of the
> > initial statements, and to a lesser degree on the operating system.
> > Icarus Verilog uses fopen(<P>,"w") to open MCD files, and in your
> > case, opening twice, the second open will truncate the first.
> >
> > It appears that VCS and ncsim agree with Icarus Verilog, at least
> > in the broader sense. Modelsim seems to be making some special effort
> > to detect that you opened the file twice and combine file descriptors,
> > which may make a small bit of sense given that mcd descriptors are
> > precious. But really, that strikes me as a lot of effort to support
> > a bad input.
> >
> > I think this situation is (and should be) left unspecified. Just
> > don't do that!-)
>
>
> ------------------------------------------------------------------------------
> Register Now for Creativity and Technology (CaT), June 3rd, NYC. CaT
> is a gathering of tech-side developers & brand creativity professionals.
> Meet
> the minds behind Google Creative Lab, Visual Complexity, Processing, &
> iPhoneDevCamp as they present alongside digital heavyweights like Barbarian
> Group, R/GA, & Big Spaceship. http://p.sf.net/sfu/creativitycat-com
> _______________________________________________
> Iverilog-devel mailing list
> Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>