iverilog-devel

[Iverilog-devel] library unisim; use unisim.vcomponents.all;

[Larry D. <ldo...@re...>]

Orson -

I'm still struggling to understand how to connect a .vhd file
that says

library unisim;
  use unisim.vcomponents.all;

with all the component declarations in

$XILINX/vhdl/src/unisims/unisim_VCOMP.vhd

and from there to the Verilog unisim implementations in
$XILINX/verilog/src/unisims/*.v.

We talked before, and I'm pretty sure that last step is
a better option than the VHDL unisim implementations in
$XILINX/vhdl/src/unisims/primitive/*.vhd.

Do you have this working?  Can you give me a recipe, or
hint, or anything?

BTW,
iverilog -g2005-sv $XILINX/vhdl/src/unisims/unisim_VCOMP.vhd
crashes and burns badly.  Hundreds of
Can't find type name `std_ulogic'
among other things.

I'm still fumbling around, maybe making a little progress.
Isn't VHDL supposed to be case-insensitive?  I can't get
an instantiation of ibufds to match a component IBUFDS.

   - Larry

Re: [Iverilog-devel] library unisim; use unisim.vcomponents.all;

[Larry D. <ldo...@re...>]

Orson -

On Fri, Jun 05, 2015 at 08:51:18PM -0700, Larry Doolittle wrote:
> I'm still struggling to understand how to connect a .vhd file
> that says
> library unisim;
>   use unisim.vcomponents.all;
> with all the component declarations in
> $XILINX/vhdl/src/unisims/unisim_VCOMP.vhd

If I can figure out how to pass "-L foo" to vhdlpp,
I think I can get through this step.  When I add that
to a by-hand invocation of vhdlpp, I can follow along
and get it to process the file
  foo/unisim/vcomponents.pkg
And if that file is a (trimmed down and hacked) copy
of $XILINX/vhdl/src/unisims/unisim_VCOMP.vhd, it seems
to emit the Verilog I'm looking for.

That still leaves my questions about std_ulogic and
case-insensitivity.

   - Larry

Re: [Iverilog-devel] library unisim; use unisim.vcomponents.all;

[Larry D. <ldo...@re...>]

Orson -

Just talking to myself on a Friday night, I guess.

On Fri, Jun 05, 2015 at 09:55:41PM -0700, Larry Doolittle wrote:
> On Fri, Jun 05, 2015 at 08:51:18PM -0700, Larry Doolittle wrote:
> > I'm still struggling to understand how to connect a .vhd file
> > that says
> > library unisim;
> >   use unisim.vcomponents.all;
> > with all the component declarations in
> > $XILINX/vhdl/src/unisims/unisim_VCOMP.vhd
> If I can figure out how to pass "-L foo" to vhdlpp,
> I think I can get through this step.

Create a what.cfg file containing
+vhdl-libdir+foo
and then a normal iverilog invocation (with the -cwhat.cfg option)
processes the file
>   foo/unisim/vcomponents.pkg

> And if that file is a (trimmed down and hacked) copy
> of $XILINX/vhdl/src/unisims/unisim_VCOMP.vhd, it seems
> to emit the Verilog I'm looking for.
> That still leaves my questions about std_ulogic and
> case-insensitivity.

The VHDL preprocessor correctly handles case-insensitive
matches between the component declaration and the instantiation.
But the Verilog it emits has the instantiation's name, ports, and
parameters/generics all converted to lower case.  This does
not match the implementation in $XILINX/verilog/src/unisims/*.v.
In fact Xilinx seems to have "standardized" on upper case for
all those names.  So the compilation as a whole fails.

I guess this is an artifact of trying to use the Verilog unisims;
if there were a chance that all the test-bench-like constructs
in their VHDL unisims would be accepted by iverilog/vhdlpp,
the case-insensitive match (as implemented by converting all VHDL
identifiers to lower case in the emitted Verilog) would work fine.

   - Larry

Re: [Iverilog-devel] library unisim; use unisim.vcomponents.all;

[Cary R. <cy...@ya...>]

Would adding an option to the VHDL config file for a given module to emit it/just the interface as upper or lower case solve your problem. I would assume the default would be lower case like we currently do. By interface I am assuming parameters, ports and the actual module name. I suppose you could argue all items in the module since most things can be accessed using various scoping rules. Though only the interface should be enough for most real examples.
 


     On Friday, June 5, 2015 10:31 PM, Larry Doolittle <ldo...@re...> wrote:
   

 Orson -

Just talking to myself on a Friday night, I guess.

On Fri, Jun 05, 2015 at 09:55:41PM -0700, Larry Doolittle wrote:
> On Fri, Jun 05, 2015 at 08:51:18PM -0700, Larry Doolittle wrote:
> > I'm still struggling to understand how to connect a .vhd file
> > that says
> > library unisim;
> >  use unisim.vcomponents.all;
> > with all the component declarations in
> > $XILINX/vhdl/src/unisims/unisim_VCOMP.vhd
> If I can figure out how to pass "-L foo" to vhdlpp,
> I think I can get through this step.

Create a what.cfg file containing
+vhdl-libdir+foo
and then a normal iverilog invocation (with the -cwhat.cfg option)
processes the file
>  foo/unisim/vcomponents.pkg

> And if that file is a (trimmed down and hacked) copy
> of $XILINX/vhdl/src/unisims/unisim_VCOMP.vhd, it seems
> to emit the Verilog I'm looking for.
> That still leaves my questions about std_ulogic and
> case-insensitivity.

The VHDL preprocessor correctly handles case-insensitive
matches between the component declaration and the instantiation.
But the Verilog it emits has the instantiation's name, ports, and
parameters/generics all converted to lower case.  This does
not match the implementation in $XILINX/verilog/src/unisims/*.v.
In fact Xilinx seems to have "standardized" on upper case for
all those names.  So the compilation as a whole fails.

I guess this is an artifact of trying to use the Verilog unisims;
if there were a chance that all the test-bench-like constructs
in their VHDL unisims would be accepted by iverilog/vhdlpp,
the case-insensitive match (as implemented by converting all VHDL
identifiers to lower case in the emitted Verilog) would work fine.

  - Larry

------------------------------------------------------------------------------
_______________________________________________
Iverilog-devel mailing list
Ive...@li...
https://lists.sourceforge.net/lists/listinfo/iverilog-devel


  

Re: [Iverilog-devel] library unisim; use unisim.vcomponents.all;

[Larry D. <ldo...@re...>]

Cary -

On Sat, Jun 06, 2015 at 08:47:56PM +0000, Cary R. wrote:
> Would adding an option to the VHDL config file for a given module to emit it/just the interface as upper or lower case solve your problem. I would assume the default would be lower case like we currently do. By interface I am assuming parameters, ports and the actual module name. I suppose you could argue all items in the module since most things can be accessed using various scoping rules. Though only the interface should be enough for most real examples.

Of 10766 parameter names in Xilinx XST 12.1 Verilog unisims, only
26 are not all-caps, and a spot check of those show they are
not part of the API.

Out of ~17117 generics and ports in unisim_VCOMP.vhd, 11 are not all-caps.
Eight of those are in one pathological component (selfheal_oserdese1_vhd).

Out of 1118 components listed in unisim_VCOMP.vhd, only four names are not
all-caps (bscntrl_iserdese1_vhd, ice_iserdese1_vhd, plg_oserdese1_vhd,
selfheal_oserdese1_vhd).

So, yes.

Maybe more work, but arguably better, would be to be case-retentive
based on the component declaration.  No need for configuration.

  - Larry

Re: [Iverilog-devel] library unisim; use unisim.vcomponents.all;

[Larry D. <ldo...@re...>]

Cary -

On Sat, Jun 06, 2015 at 04:08:22PM -0700, Larry Doolittle wrote:
> On Sat, Jun 06, 2015 at 08:47:56PM +0000, Cary R. wrote:
> > I suppose you could argue all items in the module since most things can be accessed using various scoping rules. Though only the interface should be enough for most real examples.

Xilinx and its customers consider the module name, generics,
and ports to be an API.  I've _never_ heard about anyone reaching 
into their simulations, or even talk about it.  That is not even
possible for synthesizable code, which is the focus of this VHDL work.

Just trying to agree as strongly as possible.

  - Larry

Re: [Iverilog-devel] library unisim; use unisim.vcomponents.all;

[Maciej S. <mac...@ce...>]

On 06/06/2015 06:55 AM, Larry Doolittle wrote:
> That still leaves my questions about std_ulogic and
> case-insensitivity.

As Cary suggested, I can add a patch for a configuration entry to change
letter case to either upper or lower. Preserving the original case might
be also an option, but then it can cause troubles if someone takes
advantage of VHDL's case-insensitivity.

I guess for std_ulogic the closest counterpart is "uwire logic" when it
comes to nets, but I am not sure what would be appropriate for
variables. If someone has an idea, I can also add it, this should not be
a very complex change.

Regards,
Orson