I mentioned something like this earlier. I believe Orson, needs a custom system function that scales time that is inserted into any translated code where a passed time value is used in VHDL.
Using the code he provided:
module mod(input time a);
timeunit 1ns;
timeprecision 1ps;
always @(a) begin
// this should happen after 2ns
#(a + 1ns) $display("this message should appear first (time=%t)", $time());
end
endmodule
The #(a+1ns) would be translated to something like: #($ivl_VHDL_scale_time(a)+1ns). To match Verilog like semantics the scaling would use the local time unit and precision but that may not match the VHDL semantics so maybe it is just scaled using the local unit and global precision. I am assuming the @(a) reference would also be scaled, but depending on exactly how VHDL does the time scaling this may or may not be correct (e.g. depending on the precision of the module a change in a may not trigger a change in the @() expression because of the rounding done using the $ivl_VHDL_scale_time() function if the local precision is used. The scaling would be done using the current scope calling time unit and the time unit of the caller. If a time value was passed over multiple levels this would result in a call to the function at each level.
I believe this implementation would make VHDL to VHDL and Verilog to VHDL calls work out of the box. VHDL to Verilog and possibly some Verilog to Verilog calls would require the user to scale the values, but the system function would make this mostly trivial other than remembering to use it. I expect this is a fairly obscure case so a well documented custom system function seems acceptable.
What I don't understand is the exact semantics of how VHDL handles these time variables so I'm making some assumptions that may not be correct.
On Friday, June 5, 2015 12:49 PM, Stephen Williams <st...@ic...> wrote:
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That shares the literal bits that are the time value, but it
does not account for the semantics of time. If it did, it would
scale time values to local units as they cross module boundaries.
That is the crux of the problem that Orson is facing.
On 06/05/2015 12:24 PM, Martin Whitaker wrote:
> Stephen Williams wrote:
>> You are pointing out a problem with VERILOG and not VHDL vs.
>> Verilog. In Verilog, time values do not cross module boundaries
>> through ports. Doing so will get you the headaches that you see.
>> Fixing it will involve extending the verilog language.
>>
> The SystemVerilog committee has already done this for you. See
> section 23.3.3 of 1800-2012:
>
> "Values of all data types on variables and nets can be passed
> through ports. This is accomplished by allowing both sides of a
> port connection to have assignment-compatible data types and by
> allowing continuous assignments to variables."
>
> So it is now legal to declare:
>
> module m(input time t);
>
> You can also declare:
>
> module m(ref time t);
>
> which lets you share a common variable.
>
> Martin
>
> ------------------------------------------------------------------------------
>
>
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