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From: Maciej S. <mac...@ce...> - 2015-02-19 17:07:37
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Hi Steve,
I have another update[1] along with tests[2] that brings:
- - enum can be used as a port type in modules (SystemVerilog)
- - shift operators (SRL/SLL/SRA/SLA) (VHDL)
- - labeled assignments (VHDL)
- - fixed accessing words in constant arrays of vectors (VHDL)
- - 'natural' type translated as 'int unsigned' (VHDL)
- - a bunch of minor fixes
The implementation of the fourth point may seem a bit twisted,
therefore deserves a word of explanation:
Currently, constant arrays of vectors are flattened to single
one-dimensional localparams, as there is no support for constant
unpacked arrays. Therefore, if the user wants to access a particular
word, then it is necessary to extract the adequate part of the
localparam, and it is done by adjusting the indices. Without the
adjustment, only a single bit would be returned.
To give an example:
== VHDL ==
type uns_array is array (natural range <>) of unsigned(7 downto 0);
constant const_array : uns_array(2 downto 0) :=
(0 => "00110011", 1 => "101010101", 2=> "00001111");
target_var := const_array(1);
== SystemVerilog ==
localparam const_array = { 8'b00110011, 8'b10101010, 8'b00001111 };
target_var = const_array[15:8]; // <- indices adjusted to pick the word
It can be easily changed once the unpacked constant arrays are supported.
Regards,
Orson
1. https://github.com/steveicarus/iverilog/pull/54
2. https://github.com/orsonmmz/ivtest/tree/const_array_test
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQEcBAEBCAAGBQJU5hhHAAoJEBRwGu1hpbJ1YrEIALby4wjqftFupoXI+k6OKLAk
Iz7FF265vh+oW37cKlIujAz88PWuaWkx8kIAgaK4ZQateBH5pFdypSz/vVxW8nKg
nUVvgVESxcfgFIb3Jd05PrLb86Du/eU7p5RVngAPSwkabT9DohpS6YwjoJD3N3cv
k7tEPnHLB6A4Zv7kO1yDshTF2ay23eWvK9KvbI43f8D0UwIOb7mVc0hiINnK8gdP
3icurhKWYMbCBATaOh9JgMIPSqCBUi2kW95+srJ9bOZwFu0eYu8ScmsQVe54PGnL
czcwFbc00KxhkV2J5hil0UEn/K8v8Uy3lNu5XaWhupbNefrX5ca+1QBJhJ35/98=
=kbLg
-----END PGP SIGNATURE-----
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From: Maciej S. <mac...@ce...> - 2015-03-06 19:57:51
Attachments:
signature.asc
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I had to correct the previous implementation for accessing constant
arrays of vectors. I did not realize that ranges in part selection have
to be constant, and variables are simply forbidden even if the
difference between indices is constant. This makes the solution useless
if one wants to implement e.g. a multiplexer.
New pull request [1] resolves the problem by expanding the right side
value to a concatenation of selected signals. Also, the method has been
improved to handle constant records (and arrays of records or any other
combination).
There are $ivlh_{rising,falling}_edge() VPI functions to implement
VHDL's rising_edge() and falling_edge().
Attributes are evaluated to constants whenever possible. Thanks to that
it is possible to use quite common expressions as 'left and 'right as
index. Also generic parameters are evaluated whenever possible, as I
have found at least one case where the evaluation helped.
All the mentioned changes are supported with tests [2].
Have a nice weekend,
Orson
1. https://github.com/steveicarus/iverilog/pull/55
2. https://github.com/orsonmmz/ivtest/tree/const_record_test
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From: Larry D. <ldo...@re...> - 2015-03-06 20:58:52
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Orson -
On Fri, Mar 06, 2015 at 08:57:35PM +0100, Maciej Sumiński wrote:
> I had to correct the previous implementation for accessing constant
> arrays of vectors. I did not realize that ranges in part selection have
> to be constant, and variables are simply forbidden even if the
> difference between indices is constant. This makes the solution useless
> if one wants to implement e.g. a multiplexer.
Maybe I don't fully understand the terminology, but I build
multiplexers "all the time" using indexed part select, e.g.,
module foo(
input clk,
input [3:0] ipn,
output reg [7:0] ip1
);
reg [127:0] local_data;
// stuff to set local_data not shown
always @(posedge clk) ip1 <= local_data[{ipn,3'b0}+:8];
endmodule
- Larry
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From: Stephen W. <st...@ic...> - 2015-03-06 22:14:27
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INDEXED part select can be non-constant.
The width part of index part select must be strictly constant.
Regular part select indices must be strictly constant. I think
if we don't use the work "indexed" then the part select is the
regular kind. Is that really what you mean, Orson?
On 03/06/2015 12:32 PM, Larry Doolittle wrote:
> Orson -
>
> On Fri, Mar 06, 2015 at 08:57:35PM +0100, Maciej Sumiński wrote:
>> I had to correct the previous implementation for accessing
>> constant arrays of vectors. I did not realize that ranges in part
>> selection have to be constant, and variables are simply forbidden
>> even if the difference between indices is constant. This makes
>> the solution useless if one wants to implement e.g. a
>> multiplexer.
>
> Maybe I don't fully understand the terminology, but I build
> multiplexers "all the time" using indexed part select, e.g.,
>
> module foo( input clk, input [3:0] ipn, output reg [7:0] ip1 ); reg
> [127:0] local_data; // stuff to set local_data not shown always
> @(posedge clk) ip1 <= local_data[{ipn,3'b0}+:8]; endmodule
>
> - Larry
>
> ------------------------------------------------------------------------------
>
>
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- --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iEYEARECAAYFAlT6JrgACgkQrPt1Sc2b3ilmSQCgpaNTt5LT/iIKRPt4OuczemLw
2mMAn1RUS/62mHnOppzTmDbkkAY2dtV6
=lzgP
-----END PGP SIGNATURE-----
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From: Maciej S. <mac...@ce...> - 2015-03-07 20:00:01
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-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA256 Excuse the lack of clarity. Steve got it right, I had problems with regular (non-indexed) part selects, for example: local_data[ipn+8:ipn]. I have not used indexed part select before, therefore I am grateful to Larry for his excellent suggestion. It is alread applied in the pull request [1]. Regards, Orson 1. https://github.com/orsonmmz/iverilog/commit/d1dc98b7f73c21e4eae4bde91855ef5f41059dde On 03/06/2015 11:14 PM, Stephen Williams wrote: > > INDEXED part select can be non-constant. The width part of index > part select must be strictly constant. > > Regular part select indices must be strictly constant. I think if > we don't use the work "indexed" then the part select is the regular > kind. Is that really what you mean, Orson? > > > On 03/06/2015 12:32 PM, Larry Doolittle wrote: >> Orson - > >> On Fri, Mar 06, 2015 at 08:57:35PM +0100, Maciej Sumiński wrote: >>> I had to correct the previous implementation for accessing >>> constant arrays of vectors. I did not realize that ranges in >>> part selection have to be constant, and variables are simply >>> forbidden even if the difference between indices is constant. >>> This makes the solution useless if one wants to implement e.g. >>> a multiplexer. > >> Maybe I don't fully understand the terminology, but I build >> multiplexers "all the time" using indexed part select, e.g., > >> module foo( input clk, input [3:0] ipn, output reg [7:0] ip1 ); >> reg [127:0] local_data; // stuff to set local_data not shown >> always @(posedge clk) ip1 <= local_data[{ipn,3'b0}+:8]; >> endmodule > >> - Larry > >> ------------------------------------------------------------------------------ > >> > > Dive into the World of Parallel Programming The Go Parallel > Website, sponsored >> by Intel and developed in partnership with Slashdot Media, is >> your hub for all things parallel software development, from >> weekly thought leadership blogs to news, videos, case studies, >> tutorials and more. Take a look and join the conversation now. >> http://goparallel.sourceforge.net/ >> _______________________________________________ Iverilog-devel >> mailing list Ive...@li... >> https://lists.sourceforge.net/lists/listinfo/iverilog-devel > > > > > ------------------------------------------------------------------------------ > > Dive into the World of Parallel Programming The Go Parallel Website, sponsored > by Intel and developed in partnership with Slashdot Media, is your > hub for all things parallel software development, from weekly > thought leadership blogs to news, videos, case studies, tutorials > and more. Take a look and join the conversation now. > http://goparallel.sourceforge.net/ > _______________________________________________ Iverilog-devel > mailing list Ive...@li... > https://lists.sourceforge.net/lists/listinfo/iverilog-devel > -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQEcBAEBCAAGBQJU+1i7AAoJEBRwGu1hpbJ14fEIAJFozRfOy/yObGsF41xHl9am p5nOa1QbYDZCBGCWtracH8fl5xb7L+RrIw5Kcwo57tqBwx/2gFLv7BVvdl9QP1nW HgvAENCYfvrGlVzTTkree0E2qAKQHI4y9cs/anv+E2qY3oHBDsM3hcfaBF4lyI7L DE4O8ZnpuXHKg8fRiFZwzpCDoEF5q5/yvIy5ZzoEaQlQfOIenCNoMNc6GfHl8G9b ZXnGae1BnZ0LULIGrRVY3edSEh9JUHk5U5kgcs3Dl6jW5udjjTKGeF7jzaPzov1I 61Vb/gix5L9uy62xPkzXzZE5yhe7sWbr2D+QxyP0E0qXdHcBplhv9NPHdHcVlJE= =cPlt -----END PGP SIGNATURE----- |
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