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Looks like a good plan. We should look at getting SystemVerilog to
understand resord literals (the `{...} syntax) but since it doesn't
yet, and you are generating packed structs anyhow, the regular
concatenation will work fine for now.
As for why vhdlpp emits \name instead of just name for vhdl literals?
That is because the available character set for identifiers in vhdl
and Verilog don't exactly match, so I thought it best to use Verilog
escaped names so that you can not worry about mangling VHDL names to
fit into Verilog standards.
On 09/15/2014 08:40 AM, Maciej Sumiński wrote:
> Hi Steve,
>
> I have managed to solve the problem of elaboration of constants
> initializers in packages, so there is a new pull request [1]. I
> have prepared tests too, but as we have recently agreed - I will
> merge them to the test suite repository as soon as the iverilog
> changes are merged. Now, I would like to implement elaboration for
> aggregate expressions that serve as record initializers. To
> illustrate:
>
> --- VHDL version --- library ieee; use ieee.std_logic_1164.all;
>
> entity foo_entity is end foo_entity;
>
> architecture test of foo_entity is
>
> type word is record high: std_logic_vector (3 downto 0); low:
> std_logic_vector (3 downto 0); end record;
>
> signal my_word: word := (high => "0100", low => "0110");
>
> begin my_word <= (high => "0100", low => "0110"); end test;
>
> --- SystemVerilog version --- module foo_entity; typedef struct
> packed {logic[3:0] high; logic[3:0] low;} word; wire word my_word =
> {4'b0100, 4'b0110}; // 1 //assign my_word =
> '{4'b0100, 4'b0110}; // 2 //assign my_word = '{
> high: 4'b0100, low: 4'b0110 }; // 3 assign my_word = {4'b0100,
> 4'b0110}; // 4
>
> endmodule
>
> The SystemVerilog-2012 standard says that assignment and
> initialization should be done in the way marked with "// 2". I
> have seen in a few places that it can be assigned like in "// 3",
> but could not find an excerpt in the standard that allows it.
> Icarus currently accepts and correctly executes initalization &
> assignment using the method shown in "// 1" and "// 4". Do you
> agree that I implement it that way in vhdlpp? Later it could be
> easily changed - it needs just one apostrophe to be added.
>
> By the way: I am wondering why e.g. variable names outputted by
> vhdlpp are prefixed with '\'?
>
> Regards, Orson
>
> [1] https://github.com/steveicarus/iverilog/pull/42 [2]
> https://github.com/orsonmmz/ivtest/tree/const_package_test
>
- --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
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