iverilog-devel

[Iverilog-devel] System Verilog support

[sreeraj r <sre...@ya...>]

Hi all,
          I like to start adding system-verilog support to ICARUS.. I  just added -gsystem-verilog flag to the driver in my local copy( easy   task as Steve mentioned).While going through the   lexor_keyword.gpref..., I saw two   keywords GN_KEYWORDS_ICARUS and ..1364_2005.Which one is advisable for adding sv keywords " logic" seems to be already there with -gxtypes

Can some experienced guys provide some good guidelines....( I am a n00b).I am having 6 months exp with using system verilog and with  various methodologies like ovm,vmm,etc

regards
Sreeraj R



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Re: [Iverilog-devel] System Verilog support

[Stephen W. <st...@ic...>]

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sreeraj r wrote:
> Hi all,
>           I like to start adding system-verilog support to ICARUS.. I  just added -gsystem-verilog flag to the driver in my local copy( easy   task as Steve mentioned).While going through the   lexor_keyword.gpref..., I saw two   keywords GN_KEYWORDS_ICARUS and ..1364_2005.Which one is advisable for adding sv keywords " logic" seems to be already there with -gxtypes

Neither. I'd create a new keyword category GN_KEYWORDS_1800_2005.
SystemVerilog is IEEE 1800 and you are probably working off the -2005
version. The compiler.h header file defines the keywork catagory mask
bits. The definition has comments that describe what the mask is
about, so you should see that you can select a bit and define your
new GN_KEYWORDS_* to use that bit. Then when you add your keywords
to the lexor_keywords.gperf file, use your bit.

> Can some experienced guys provide some good guidelines....( I am a n00b).I am having 6 months exp with using system verilog and with  various methodologies like ovm,vmm,etc

SystemVerilog support is a *big* task. You'll be at it for a while;-)
If you haven't already done so, make sure you've read through and
understood the Developer Guide on the iverilog.wikia.com documentation
wiki.
- --
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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Comment: Using GnuPG with SUSE - http://enigmail.mozdev.org

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Re: [Iverilog-devel] System Verilog support

[Cary R. <cy...@ya...>]

My suggestion would be to work on adding something simple to get
a feel for how things work in Icarus and what is involved in
adding functionality to the compiler and run time. Missing data
types or possibly assertions may be a good place to start. If
there is some SV construct that you would really like to use
propose that and Steve or I can give you some suggestions.
Certain things may require a substantial change to Icarus, but
many features can be added incrementally. Full SV, like Steve
said, is going to be a significant effort.

Cary


      

Re: [Iverilog-devel] System Verilog support

[sreeraj r <sre...@ya...>]

Hi Cary/Steve/Kev,

I have added -gsystem-verilog flags and submitted a patch in the tracker. I would like to take up that system verilog time literals addition task and adding assertion support ( I have played a lot with assertions in my projects and love to see that feature in Icarus.  ).

waiting for valuable feedback ( Do you guys hang around any of the irc channels.)
Sreeraj 




________________________________
From: Cary R. <cy...@ya...>
To: Discussions concerning Icarus Verilog development <ive...@li...>
Sent: Monday, 17 November, 2008 11:11:07 PM
Subject: Re: [Iverilog-devel] System Verilog support

My suggestion would be to work on adding something simple to get
a feel for how things work in Icarus and what is involved in
adding functionality to the compiler and run time. Missing data
types or possibly assertions may be a good place to start. If
there is some SV construct that you would really like to use
propose that and Steve or I can give you some suggestions.
Certain things may require a substantial change to Icarus, but
many features can be added incrementally. Full SV, like Steve
said, is going to be a significant effort.

Cary


      

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Re: [Iverilog-devel] System Verilog support

[Cary R. <cy...@ya...>]

--- On Sat, 1/10/09, sreeraj r <sre...@ya...> wrote:

> I have added -gsystem-verilog flags and submitted a patch
> in the tracker. I would like to take up that system verilog
> time literals addition task and adding assertion support ( I
> have played a lot with assertions in my projects and love to
> see that feature in Icarus.  ).

I would love to see the assertions, but it may be easier to
add the time literals first.

Before you go down that path I have a couple of System-verilog
questions. If you have a netlist that is using `timescale 1ns/1ps
what happens if you encounter a delay of 100fs? Does the
simulator need to notice this during compilation and change the
minimum time step (precision) to 100fS or is it safe to make this
a #0 delay? I'm not certain we want to just drop the delay for
this case. Hopefully the standard provides some insight.

If all this works out right you may be able to just recode
the PDelay class and the parser/lexor to handle the new
constants and then when calculate_val() is called it uses
the constants time unit vs the current time unit to scale
the constant to a system unit delay (based on the precision).

Even if the 100fS does set the minimum time step This is
just a slight modification in that you need to make the
design precision be based on this. I'm guessing that this
is not the case, but since I don't have a copy of the
standard you will need to figure out what is the correct
behavior.

If you would prefer to work on the assert statements first
let us know and we can provide some pointers on things to
consider when implementing them. I will nee to look at the
code with assert in mind before I can make too many
recommendations.

> waiting for valuable feedback ( Do you guys hang around any
> of the irc channels.)

Not normally. I'm usually busy working at my day job or fixing
bugs in Icarus and for the most part I prefer to minimize the
interruptions when doing either.


      

Re: [Iverilog-devel] System Verilog support

[Kevin C. <iv...@gr...>]

There isn't really a requirement that "logic" is a keyword, it's just a 
type-name. SV's type system is bad, if you want to go down the road of 
supporting it, I'd suggest giving yourself a layer of abstraction and do 
some lower level definitions from which you can derive the "logic" type 
with typedefs etc.. E.g. you can consider the base type of logic to be a 
4-value enum, and if you have a template "bit" class for handling logic 
wires you can say something like:

   enum logic_4state {lo,hi,x,z};
   typedef bit<logic_4state> logic;

The upside of that is the code is polymorphic and you can use the same 
(System)Verilog with different type definitions more easily.
 
Some other objects in Verilog are really better defined through 
templates and typedefs, e.g. a "reg" is really a driver object of type 
"logic", so if you have a template driver class you could say something 
like:

    typedef driver<logic> reg;

- which would be backward compatible and means that "reg" is just a 
type-name and not a keyword. In that vein you can then do something like:

   typedef driver<bool> breg;

- for a 2-state driver.

For mixed signal stuff I like to consider signals as having three 
orthogonal values: level, strength and certainty, so for logic I prefer 
a representation based on three bool values, so I would prefer to define 
logic as (say):

   typedef ms_bit<bool,bool,bool> logic;

- where one bool represents the level (1/0) another the strengh (driven 
or undriven), and the third if the value is known (x or not). That way I 
can get different behavior out of the same Verilog without changing the 
source, and I can more easily mix different representations within a design.

You're going to have to do all the typedef/template stuff if you want to 
support SV, so you might as well take advantage of it.

Just some thoughts,
Kev.

Stephen Williams wrote:
> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA1
>
> sreeraj r wrote:
>   
>> Hi all,
>>           I like to start adding system-verilog support to ICARUS.. I  just added -gsystem-verilog flag to the driver in my local copy( easy   task as Steve mentioned).While going through the   lexor_keyword.gpref..., I saw two   keywords GN_KEYWORDS_ICARUS and ..1364_2005.Which one is advisable for adding sv keywords " logic" seems to be already there with -gxtypes
>>     
>
> Neither. I'd create a new keyword category GN_KEYWORDS_1800_2005.
> SystemVerilog is IEEE 1800 and you are probably working off the -2005
> version. The compiler.h header file defines the keywork catagory mask
> bits. The definition has comments that describe what the mask is
> about, so you should see that you can select a bit and define your
> new GN_KEYWORDS_* to use that bit. Then when you add your keywords
> to the lexor_keywords.gperf file, use your bit.
>
>   
>> Can some experienced guys provide some good guidelines....( I am a n00b).I am having 6 months exp with using system verilog and with  various methodologies like ovm,vmm,etc
>>     
>
> SystemVerilog support is a *big* task. You'll be at it for a while;-)
> If you haven't already done so, make sure you've read through and
> understood the Developer Guide on the iverilog.wikia.com documentation
> wiki.
> - --
> Steve Williams                "The woods are lovely, dark and deep.
> steve at icarus.com           But I have promises to keep,
> http://www.icarus.com         and lines to code before I sleep,
> http://www.picturel.com       And lines to code before I sleep."
> -----BEGIN PGP SIGNATURE-----
> Version: GnuPG v2.0.4-svn0 (GNU/Linux)
> Comment: Using GnuPG with SUSE - http://enigmail.mozdev.org
>
> iD8DBQFJIahxrPt1Sc2b3ikRAu1lAKDXvQe3I8wqR61h0w1KMdcGUR/q/QCbBfQP
> 22XsSFeM1g4gSTUwTJh0K5k=
> =Le+r
> -----END PGP SIGNATURE-----
>
> -------------------------------------------------------------------------
> This SF.Net email is sponsored by the Moblin Your Move Developer's challenge
> Build the coolest Linux based applications with Moblin SDK & win great prizes
> Grand prize is a trip for two to an Open Source event anywhere in the world
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