iverilog-devel

[Iverilog-devel] assign/deassign and force/release of bit/part selects.

[Cary R. <cy...@ya...>]

I'm working on the implementation for assign/deassign of bit and part
selects and decided to see what the standard had to say. Very interesting!

For reference this is what it says about assign (section 9.3 page 125
1364-2001):

The left-hand side of the assignment in the assign statement shall be a
variable reference or a concatenation of variables. It shall not be a
memory word (array reference) or a bit-select or a part-select of a
variable.

The way I read this is that an assign only works on a register/etc. type
not a wire (net). The standard say we shouldn't allow an assign to an
array word, but we don't distinguish between individual array words and a
normal variable. Bit and part selects are not allowed, but I'm working on
implementing them.

It says basically the same think for force except it allows force to work
on either variables or nets. Though it is missing the array word
exclusion. 

Can someone look at 2005 and see if it says anything different. Do we
still want this functionality as an enhancement? For now I'm assuming we
do. If nothing else to make force and assign match.

Cary


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Re: [Iverilog-devel] assign/deassign and force/release of bit/part selects.

[Larry D. <ldo...@re...>]

Cary -

On Tue, Apr 08, 2008 at 05:29:01PM -0700, Cary R. wrote:
> The left-hand side of the assignment in the assign statement shall be a
> variable reference or a concatenation of variables. It shall not be a
> memory word (array reference) or a bit-select or a part-select of a
> variable.
> 
> The way I read this is that an assign only works on a register/etc. type
> not a wire (net).

You have to let me assign to a wire.
All Verilog code that I've seen is full of that construct.

   - Larry

Re: [Iverilog-devel] assign/deassign and force/release of bit/part selects.

[Cary R. <cy...@ya...>]

--- Larry Doolittle <ldo...@re...> wrote:
 
> You have to let me assign to a wire.
> All Verilog code that I've seen is full of that construct.

I guess I forgot to mention this is for a procedural assign:

initial begin
  rval = 1'b0;
  #1 assign rval = 1'b1;
  #1 deassign rval;
end

This has nothing to do with a normal continuous assignment which only
works on wires.

Cary


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Re: [Iverilog-devel] assign/deassign and force/release of bit/part selects.

[Stephen W. <st...@ic...>]

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Cary R. wrote:
> I'm working on the implementation for assign/deassign of bit and part
> selects and decided to see what the standard had to say. Very interesting!
> 
> For reference this is what it says about assign (section 9.3 page 125
> 1364-2001):
> 
> The left-hand side of the assignment in the assign statement shall be a
> variable reference or a concatenation of variables. It shall not be a
> memory word (array reference) or a bit-select or a part-select of a
> variable.

It says the same thing. I understand why they disallow memory words,
and we should stick with that. I'm surprised about the bit/part
select exclusion, but given the trouble *we* are having with it,
I can understand why it is there;-)

> The way I read this is that an assign only works on a register/etc. type
> not a wire (net). The standard say we shouldn't allow an assign to an
> array word, but we don't distinguish between individual array words and a
> normal variable. Bit and part selects are not allowed, but I'm working on
> implementing them.
> 
> It says basically the same think for force except it allows force to work
> on either variables or nets. Though it is missing the array word
> exclusion. 

The 2005 spec is explicit that it should not allow memory words
or array references. I think we *can* allow array references if
the address expression is constant. I think that would be more
interesting then adding assign/deassign to bit/part selects.

As for accepting assign/deassign of bit/part select, I guess we
can add support to them if it is not too hard. We may want to
think about adding a warning type "extensions" that would flag
this sort of thing so that people can vet their code for portability.

- --
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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Re: [Iverilog-devel] assign/deassign and force/release of bit/part selects.

[Cary R. <cy...@ya...>]

--- Stephen Williams <st...@ic...> wrote:

> As for accepting assign/deassign of bit/part select, I guess we
> can add support to them if it is not too hard. We may want to
> think about adding a warning type "extensions" that would flag
> this sort of thing so that people can vet their code for portability.

assign appears to be finished and deassign is almost there. If we are
going to have a warning of this we should also add it for force and
release. I'll have to look and see what array words do.

Cary


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Re: [Iverilog-devel] assign/deassign and force/release of bit/part selects.

[Cary R. <cy...@ya...>]

It appears I have this working correctly for vec4. I need to fix the vec8
code and my test uncovered a compiler optimization that in the context of
assign (and force) is not correct.

If you assign a value to a variable you cannot use the thread bits you
just used to assign as the value since a continuous assignment may not
allow the assignment to work correctly. I had noticed this in the test for
bit/part select release. I just didn't track the problem down.

Cary


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