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Steven Wilson wrote:
> Okay - I'm subscribed as a lurker on the iverilog-devel list.
Moving this conversation there, then, because it is of general
interesting I think.
> There are certainly some things I like right away [about system Verilog].
> while others seem
> pointless (logic versus reg..) The tutorial I read said the justification
> for logic - "It's just better."
"logic" and "reg", and also "bool" types should be entirely doable.
In fact, Icarus Verilog already supports logic and bool somewhat, and
also allows for real value nets as well in places that Verilog does not.
We are busy working on fixing bugs there, though. It would be pretty
kool too to add support for enumerations all the way through to the
gtkwave viewer. That would solve a problem that a *lot* of Verilog
users gripe about: Marking traces with useful names.
> I particularly like always_ff, always_comb, and always_latch. This is from
> a "How did that latch get there" point of view in synthesis.
Entirely doable in Icarus Verilog. They can also be used to constrain
user expectations and thus lead to better warnings from the compiler.
I personally support adding those statements.
- --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
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