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From: Lonnie L G. <lg...@sr...> - 2016-01-12 17:27:13
|
I ran into some verilog code that iverilog is failing to compile but vcs
does.
It appears the problem is having the reg on the right side of an
instantiation.
If I comment out the line .wen (rmw_busy_fifo_wen) it compiles.
Or if I assign rmw_busy_fifo_wen to a wire and set .wen to the wire it
compiles.
I have several of these in one module and they all fail the same.
Here are the iverilog errors:
/home/lgliem/macros/carte/cntrlr_if/map_m/llvm_user_obm_bank_if_mapl.v:2066:
error: rmw_busy_fifo_wen Unable to assign to unresolved wires.
/home/lgliem/macros/carte/cntrlr_if/map_m/llvm_user_obm_bank_if_mapl.v:2068:
error: rmw_busy_fifo_wen Unable to assign to unresolved wires.
Thanks
Lonnie
reg rmw_busy_fifo_wen;
always @ (posedge sysclk or posedge user_reset)
if (user_reset)
rmw_busy_fifo_wen <= 1'b0; <----- this is line 2066
else
rmw_busy_fifo_wen <= ((request_valid_d2 & (set_obm_busy | obm_busy)) |
<--- this is 2067
(set_normal_wr_patha & (obm_read | obm_read_d1)));
llvm_mapl_blockram_sync_8x93bit rmw_busy_fifo (
.out (rmw_busy_fifo_rd[92:00]),
.almost_empty (rmw_busy_fifo_almost_empty),
.empty (rmw_busy_fifo_empty),
.data_valid (rmw_busy_fifo_valid),
.almost_full (rmw_busy_fifo_full),
.inbit (rmw_busy_fifo_wrdata[92:0]),
.ren (rmw_busy_fifo_ren),
.wen (rmw_busy_fifo_wen),
.ce (1'b1),
.clk (sysclk),
.rst (user_reset)
);
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From: Iztok J. <izt...@gm...> - 2016-01-12 18:21:06
|
Hi, Could you check the direction of the 'wen' port inside the module llvm_mapl_blockram_sync_8x93bit? And perhaps if there are any asignments to the wen signal inside the module. Some simulators ignore signal directions, but check for multiple drivers. So although the direction is wrong, the design might be functionally correct. Regards, Iztok Jeras On Tue, Jan 12, 2016 at 6:10 PM, Lonnie L Gliem <lg...@sr...> wrote: > I ran into some verilog code that iverilog is failing to compile but vcs > > does. > > > > It appears the problem is having the reg on the right side of an > instantiation. > > If I comment out the line .wen (rmw_busy_fifo_wen) it compiles. > > > > Or if I assign rmw_busy_fifo_wen to a wire and set .wen to the wire it > compiles. > > > > I have several of these in one module and they all fail the same. > > > > Here are the iverilog errors: > > > /home/lgliem/macros/carte/cntrlr_if/map_m/llvm_user_obm_bank_if_mapl.v:2066: > > error: rmw_busy_fifo_wen Unable to assign to unresolved wires. > > > /home/lgliem/macros/carte/cntrlr_if/map_m/llvm_user_obm_bank_if_mapl.v:2068: > > error: rmw_busy_fifo_wen Unable to assign to unresolved wires. > > > > Thanks > > Lonnie > > > > reg rmw_busy_fifo_wen; > > > > always @ (posedge sysclk or posedge user_reset) > > if (user_reset) > > rmw_busy_fifo_wen <= 1'b0; <----- this is line 2066 > > else > > rmw_busy_fifo_wen <= ((request_valid_d2 & (set_obm_busy | obm_busy)) > | <--- this is 2067 > > > (set_normal_wr_patha & (obm_read | obm_read_d1))); > > > > llvm_mapl_blockram_sync_8x93bit rmw_busy_fifo ( > > .out (rmw_busy_fifo_rd[92:00]), > > .almost_empty (rmw_busy_fifo_almost_empty), > > .empty (rmw_busy_fifo_empty), > > .data_valid (rmw_busy_fifo_valid), > > .almost_full (rmw_busy_fifo_full), > > .inbit (rmw_busy_fifo_wrdata[92:0]), > > .ren (rmw_busy_fifo_ren), > > .wen (rmw_busy_fifo_wen), > > .ce (1'b1), > > .clk (sysclk), > > .rst (user_reset) > > ); > > > > > ------------------------------------------------------------------------------ > Site24x7 APM Insight: Get Deep Visibility into Application Performance > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month > Monitor end-to-end web transactions and take corrective actions now > Troubleshoot faster and improve end-user experience. Signup Now! > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 > _______________________________________________ > Iverilog-devel mailing list > Ive...@li... > https://lists.sourceforge.net/lists/listinfo/iverilog-devel > > |
|
From: Larry D. <ldo...@re...> - 2016-01-12 18:43:34
|
Lonnie - On Tue, Jan 12, 2016 at 11:10:39AM -0600, Lonnie L Gliem wrote: > I ran into some verilog code that iverilog is failing to compile but vcs > does. The snippets you posted look good to me, iverilog should have no problem with that. Can you post a stand-alone test case that reproduces the error? - Larry |
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From: Lonnie G. <lg...@sr...> - 2016-01-12 18:48:19
|
It is an input.
module llvm_mapl_blockram_sync_8x93bit (
output wire [92:0] out,
output reg almost_empty,
output reg empty,
output reg data_valid,
output reg almost_full,
input [92:0] inbit,
input ren,
input wen,
input ce,
input clk,
input rst
);
I will try and cut it down to s small testcase but it may take a bit it
is quite large.
Lonnie
On Tue, Jan 12, 2016 at 07:20:59PM +0100, Iztok Jeras wrote:
> Hi,
>
> Could you check the direction of the 'wen' port inside the
> module llvm_mapl_blockram_sync_8x93bit? And perhaps if there are any
> asignments to the wen signal inside the module.
>
> Some simulators ignore signal directions, but check for multiple drivers.
> So although the direction is wrong, the design might be functionally
> correct.
>
> Regards,
> Iztok Jeras
>
> On Tue, Jan 12, 2016 at 6:10 PM, Lonnie L Gliem <lg...@sr...>
> wrote:
>
> > I ran into some verilog code that iverilog is failing to compile but vcs
> >
> > does.
> >
> >
> >
> > It appears the problem is having the reg on the right side of an
> > instantiation.
> >
> > If I comment out the line .wen (rmw_busy_fifo_wen) it compiles.
> >
> >
> >
> > Or if I assign rmw_busy_fifo_wen to a wire and set .wen to the wire it
> > compiles.
> >
> >
> >
> > I have several of these in one module and they all fail the same.
> >
> >
> >
> > Here are the iverilog errors:
> >
> >
> > /home/lgliem/macros/carte/cntrlr_if/map_m/llvm_user_obm_bank_if_mapl.v:2066:
> >
> > error: rmw_busy_fifo_wen Unable to assign to unresolved wires.
> >
> >
> > /home/lgliem/macros/carte/cntrlr_if/map_m/llvm_user_obm_bank_if_mapl.v:2068:
> >
> > error: rmw_busy_fifo_wen Unable to assign to unresolved wires.
> >
> >
> >
> > Thanks
> >
> > Lonnie
> >
> >
> >
> > reg rmw_busy_fifo_wen;
> >
> >
> >
> > always @ (posedge sysclk or posedge user_reset)
> >
> > if (user_reset)
> >
> > rmw_busy_fifo_wen <= 1'b0; <----- this is line 2066
> >
> > else
> >
> > rmw_busy_fifo_wen <= ((request_valid_d2 & (set_obm_busy | obm_busy))
> > | <--- this is 2067
> >
> >
> > (set_normal_wr_patha & (obm_read | obm_read_d1)));
> >
> >
> >
> > llvm_mapl_blockram_sync_8x93bit rmw_busy_fifo (
> >
> > .out (rmw_busy_fifo_rd[92:00]),
> >
> > .almost_empty (rmw_busy_fifo_almost_empty),
> >
> > .empty (rmw_busy_fifo_empty),
> >
> > .data_valid (rmw_busy_fifo_valid),
> >
> > .almost_full (rmw_busy_fifo_full),
> >
> > .inbit (rmw_busy_fifo_wrdata[92:0]),
> >
> > .ren (rmw_busy_fifo_ren),
> >
> > .wen (rmw_busy_fifo_wen),
> >
> > .ce (1'b1),
> >
> > .clk (sysclk),
> >
> > .rst (user_reset)
> >
> > );
> >
> >
> >
> >
> > ------------------------------------------------------------------------------
> > Site24x7 APM Insight: Get Deep Visibility into Application Performance
> > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
> > Monitor end-to-end web transactions and take corrective actions now
> > Troubleshoot faster and improve end-user experience. Signup Now!
> > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140
> > _______________________________________________
> > Iverilog-devel mailing list
> > Ive...@li...
> > https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> >
> >
> ------------------------------------------------------------------------------
> Site24x7 APM Insight: Get Deep Visibility into Application Performance
> APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
> Monitor end-to-end web transactions and take corrective actions now
> Troubleshoot faster and improve end-user experience. Signup Now!
> http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140
> _______________________________________________
> Iverilog-devel mailing list
> Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
|
|
From: Iztok J. <izt...@gm...> - 2016-01-12 19:54:37
|
for now could jou just grep all lines containing wen inside llvm_mapl_blockram_sync_8x93bit $ grep wen llvm_mapl_blockram_sync_8x93bit.v On Tue, Jan 12, 2016 at 7:47 PM, Lonnie Gliem <lg...@sr...> wrote: > It is an input. > > module llvm_mapl_blockram_sync_8x93bit ( > output wire [92:0] out, > output reg almost_empty, > output reg empty, > output reg data_valid, > output reg almost_full, > input [92:0] inbit, > input ren, > input wen, > input ce, > input clk, > input rst > ); > > I will try and cut it down to s small testcase but it may take a bit it > is quite large. > > Lonnie > > On Tue, Jan 12, 2016 at 07:20:59PM +0100, Iztok Jeras wrote: > > Hi, > > > > Could you check the direction of the 'wen' port inside the > > module llvm_mapl_blockram_sync_8x93bit? And perhaps if there are any > > asignments to the wen signal inside the module. > > > > Some simulators ignore signal directions, but check for multiple drivers. > > So although the direction is wrong, the design might be functionally > > correct. > > > > Regards, > > Iztok Jeras > > > > On Tue, Jan 12, 2016 at 6:10 PM, Lonnie L Gliem <lg...@sr... > > > > wrote: > > > > > I ran into some verilog code that iverilog is failing to compile but > vcs > > > > > > does. > > > > > > > > > > > > It appears the problem is having the reg on the right side of an > > > instantiation. > > > > > > If I comment out the line .wen (rmw_busy_fifo_wen) it compiles. > > > > > > > > > > > > Or if I assign rmw_busy_fifo_wen to a wire and set .wen to the wire it > > > compiles. > > > > > > > > > > > > I have several of these in one module and they all fail the same. > > > > > > > > > > > > Here are the iverilog errors: > > > > > > > > > > /home/lgliem/macros/carte/cntrlr_if/map_m/llvm_user_obm_bank_if_mapl.v:2066: > > > > > > error: rmw_busy_fifo_wen Unable to assign to unresolved wires. > > > > > > > > > > /home/lgliem/macros/carte/cntrlr_if/map_m/llvm_user_obm_bank_if_mapl.v:2068: > > > > > > error: rmw_busy_fifo_wen Unable to assign to unresolved wires. > > > > > > > > > > > > Thanks > > > > > > Lonnie > > > > > > > > > > > > reg rmw_busy_fifo_wen; > > > > > > > > > > > > always @ (posedge sysclk or posedge user_reset) > > > > > > if (user_reset) > > > > > > rmw_busy_fifo_wen <= 1'b0; <----- this is line 2066 > > > > > > else > > > > > > rmw_busy_fifo_wen <= ((request_valid_d2 & (set_obm_busy | > obm_busy)) > > > | <--- this is 2067 > > > > > > > > > (set_normal_wr_patha & (obm_read | obm_read_d1))); > > > > > > > > > > > > llvm_mapl_blockram_sync_8x93bit rmw_busy_fifo ( > > > > > > .out (rmw_busy_fifo_rd[92:00]), > > > > > > .almost_empty (rmw_busy_fifo_almost_empty), > > > > > > .empty (rmw_busy_fifo_empty), > > > > > > .data_valid (rmw_busy_fifo_valid), > > > > > > .almost_full (rmw_busy_fifo_full), > > > > > > .inbit > (rmw_busy_fifo_wrdata[92:0]), > > > > > > .ren (rmw_busy_fifo_ren), > > > > > > .wen (rmw_busy_fifo_wen), > > > > > > .ce (1'b1), > > > > > > .clk (sysclk), > > > > > > .rst (user_reset) > > > > > > ); > > > > > > > > > > > > > > > > ------------------------------------------------------------------------------ > > > Site24x7 APM Insight: Get Deep Visibility into Application Performance > > > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month > > > Monitor end-to-end web transactions and take corrective actions now > > > Troubleshoot faster and improve end-user experience. Signup Now! > > > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 > > > _______________________________________________ > > > Iverilog-devel mailing list > > > Ive...@li... > > > https://lists.sourceforge.net/lists/listinfo/iverilog-devel > > > > > > > > > > ------------------------------------------------------------------------------ > > Site24x7 APM Insight: Get Deep Visibility into Application Performance > > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month > > Monitor end-to-end web transactions and take corrective actions now > > Troubleshoot faster and improve end-user experience. Signup Now! > > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 > > _______________________________________________ > > Iverilog-devel mailing list > > Ive...@li... > > https://lists.sourceforge.net/lists/listinfo/iverilog-devel > > > > ------------------------------------------------------------------------------ > Site24x7 APM Insight: Get Deep Visibility into Application Performance > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month > Monitor end-to-end web transactions and take corrective actions now > Troubleshoot faster and improve end-user experience. Signup Now! > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 > _______________________________________________ > Iverilog-devel mailing list > Ive...@li... > https://lists.sourceforge.net/lists/listinfo/iverilog-devel > |
|
From: Martin W. <mai...@ma...> - 2016-01-12 19:54:41
Attachments:
bug.v
|
Lonnie L Gliem wrote: > I ran into some verilog code that iverilog is failing to compile but vcs > does. > The error message you are getting suggests: 1) There is a continuous assignment to rmw_busy_fifo_wen somewhere in your code. 2) You are instructing iverilog to compile SystemVerilog code. I can reproduce your error with the attached simple test case, which results in: % iverilog -g2012 bug.v bug.v:13: error: q Unable to assign to unresolved wires. bug.v:15: error: q Unable to assign to unresolved wires. 2 error(s) during elaboration. If the continuous assignment is inside the sub module, you should also get a warning like: bug.v:18: warning: input port w is coerced to inout. If compiled without the -g2012 option, you get a more helpful error: % iverilog bug.v bug.v:9: error: reg q; cannot be driven by primitives or continuous assignment. 1 error(s) during elaboration. If either of the above two conditions aren't true, it's likely a compiler bug, and we are going to need a failing test case to analyse. Martin |
|
From: Lonnie G. <lg...@sr...> - 2016-01-12 20:19:22
|
Not much on the grep I don't see any continuous assignments.
$ grep wen
/temp/builds/150918-0934/carte/macros/carte/cntrlr_if/map_m/llvm_mapl_blockram_sync_8x93bit.v
input wen,
.ce (wen)
.wren (wen),
Lonnie
On Tue, Jan 12, 2016 at 08:54:29PM +0100, Iztok Jeras wrote:
> for now could jou just grep all lines containing wen
> inside llvm_mapl_blockram_sync_8x93bit
>
> $ grep wen llvm_mapl_blockram_sync_8x93bit.v
>
> On Tue, Jan 12, 2016 at 7:47 PM, Lonnie Gliem <lg...@sr...>
> wrote:
>
> > It is an input.
> >
> > module llvm_mapl_blockram_sync_8x93bit (
> > output wire [92:0] out,
> > output reg almost_empty,
> > output reg empty,
> > output reg data_valid,
> > output reg almost_full,
> > input [92:0] inbit,
> > input ren,
> > input wen,
> > input ce,
> > input clk,
> > input rst
> > );
> >
> > I will try and cut it down to s small testcase but it may take a bit it
> > is quite large.
> >
> > Lonnie
> >
> > On Tue, Jan 12, 2016 at 07:20:59PM +0100, Iztok Jeras wrote:
> > > Hi,
> > >
> > > Could you check the direction of the 'wen' port inside the
> > > module llvm_mapl_blockram_sync_8x93bit? And perhaps if there are any
> > > asignments to the wen signal inside the module.
> > >
> > > Some simulators ignore signal directions, but check for multiple drivers.
> > > So although the direction is wrong, the design might be functionally
> > > correct.
> > >
> > > Regards,
> > > Iztok Jeras
> > >
> > > On Tue, Jan 12, 2016 at 6:10 PM, Lonnie L Gliem <lg...@sr...
> > >
> > > wrote:
> > >
> > > > I ran into some verilog code that iverilog is failing to compile but
> > vcs
> > > >
> > > > does.
> > > >
> > > >
> > > >
> > > > It appears the problem is having the reg on the right side of an
> > > > instantiation.
> > > >
> > > > If I comment out the line .wen (rmw_busy_fifo_wen) it compiles.
> > > >
> > > >
> > > >
> > > > Or if I assign rmw_busy_fifo_wen to a wire and set .wen to the wire it
> > > > compiles.
> > > >
> > > >
> > > >
> > > > I have several of these in one module and they all fail the same.
> > > >
> > > >
> > > >
> > > > Here are the iverilog errors:
> > > >
> > > >
> > > >
> > /home/lgliem/macros/carte/cntrlr_if/map_m/llvm_user_obm_bank_if_mapl.v:2066:
> > > >
> > > > error: rmw_busy_fifo_wen Unable to assign to unresolved wires.
> > > >
> > > >
> > > >
> > /home/lgliem/macros/carte/cntrlr_if/map_m/llvm_user_obm_bank_if_mapl.v:2068:
> > > >
> > > > error: rmw_busy_fifo_wen Unable to assign to unresolved wires.
> > > >
> > > >
> > > >
> > > > Thanks
> > > >
> > > > Lonnie
> > > >
> > > >
> > > >
> > > > reg rmw_busy_fifo_wen;
> > > >
> > > >
> > > >
> > > > always @ (posedge sysclk or posedge user_reset)
> > > >
> > > > if (user_reset)
> > > >
> > > > rmw_busy_fifo_wen <= 1'b0; <----- this is line 2066
> > > >
> > > > else
> > > >
> > > > rmw_busy_fifo_wen <= ((request_valid_d2 & (set_obm_busy |
> > obm_busy))
> > > > | <--- this is 2067
> > > >
> > > >
> > > > (set_normal_wr_patha & (obm_read | obm_read_d1)));
> > > >
> > > >
> > > >
> > > > llvm_mapl_blockram_sync_8x93bit rmw_busy_fifo (
> > > >
> > > > .out (rmw_busy_fifo_rd[92:00]),
> > > >
> > > > .almost_empty (rmw_busy_fifo_almost_empty),
> > > >
> > > > .empty (rmw_busy_fifo_empty),
> > > >
> > > > .data_valid (rmw_busy_fifo_valid),
> > > >
> > > > .almost_full (rmw_busy_fifo_full),
> > > >
> > > > .inbit
> > (rmw_busy_fifo_wrdata[92:0]),
> > > >
> > > > .ren (rmw_busy_fifo_ren),
> > > >
> > > > .wen (rmw_busy_fifo_wen),
> > > >
> > > > .ce (1'b1),
> > > >
> > > > .clk (sysclk),
> > > >
> > > > .rst (user_reset)
> > > >
> > > > );
> > > >
> > > >
> > > >
> > > >
> > > >
> > ------------------------------------------------------------------------------
> > > > Site24x7 APM Insight: Get Deep Visibility into Application Performance
> > > > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
> > > > Monitor end-to-end web transactions and take corrective actions now
> > > > Troubleshoot faster and improve end-user experience. Signup Now!
> > > > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140
> > > > _______________________________________________
> > > > Iverilog-devel mailing list
> > > > Ive...@li...
> > > > https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> > > >
> > > >
> >
> > >
> > ------------------------------------------------------------------------------
> > > Site24x7 APM Insight: Get Deep Visibility into Application Performance
> > > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
> > > Monitor end-to-end web transactions and take corrective actions now
> > > Troubleshoot faster and improve end-user experience. Signup Now!
> > > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140
> > > _______________________________________________
> > > Iverilog-devel mailing list
> > > Ive...@li...
> > > https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> >
> >
> >
> > ------------------------------------------------------------------------------
> > Site24x7 APM Insight: Get Deep Visibility into Application Performance
> > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
> > Monitor end-to-end web transactions and take corrective actions now
> > Troubleshoot faster and improve end-user experience. Signup Now!
> > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140
> > _______________________________________________
> > Iverilog-devel mailing list
> > Ive...@li...
> > https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> >
> ------------------------------------------------------------------------------
> Site24x7 APM Insight: Get Deep Visibility into Application Performance
> APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
> Monitor end-to-end web transactions and take corrective actions now
> Troubleshoot faster and improve end-user experience. Signup Now!
> http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140
> _______________________________________________
> Iverilog-devel mailing list
> Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
|
|
From: Iztok J. <izt...@gm...> - 2016-01-12 20:48:42
|
you should further check if both 'ce' and 'wren' ports are inputs, and that the signals are not driven inside those modules On Tue, Jan 12, 2016 at 9:18 PM, Lonnie Gliem <lg...@sr...> wrote: > Not much on the grep I don't see any continuous assignments. > > $ grep wen > > /temp/builds/150918-0934/carte/macros/carte/cntrlr_if/map_m/llvm_mapl_blockram_sync_8x93bit.v > input wen, > .ce (wen) > .wren (wen), > > Lonnie > > On Tue, Jan 12, 2016 at 08:54:29PM +0100, Iztok Jeras wrote: > > for now could jou just grep all lines containing wen > > inside llvm_mapl_blockram_sync_8x93bit > > > > $ grep wen llvm_mapl_blockram_sync_8x93bit.v > > > > On Tue, Jan 12, 2016 at 7:47 PM, Lonnie Gliem <lg...@sr...> > > wrote: > > > > > It is an input. > > > > > > module llvm_mapl_blockram_sync_8x93bit ( > > > output wire [92:0] out, > > > output reg almost_empty, > > > output reg empty, > > > output reg data_valid, > > > output reg almost_full, > > > input [92:0] inbit, > > > input ren, > > > input wen, > > > input ce, > > > input clk, > > > input rst > > > ); > > > > > > I will try and cut it down to s small testcase but it may take a bit it > > > is quite large. > > > > > > Lonnie > > > > > > On Tue, Jan 12, 2016 at 07:20:59PM +0100, Iztok Jeras wrote: > > > > Hi, > > > > > > > > Could you check the direction of the 'wen' port inside the > > > > module llvm_mapl_blockram_sync_8x93bit? And perhaps if there are any > > > > asignments to the wen signal inside the module. > > > > > > > > Some simulators ignore signal directions, but check for multiple > drivers. > > > > So although the direction is wrong, the design might be functionally > > > > correct. > > > > > > > > Regards, > > > > Iztok Jeras > > > > > > > > On Tue, Jan 12, 2016 at 6:10 PM, Lonnie L Gliem < > lg...@sr... > > > > > > > > wrote: > > > > > > > > > I ran into some verilog code that iverilog is failing to compile > but > > > vcs > > > > > > > > > > does. > > > > > > > > > > > > > > > > > > > > It appears the problem is having the reg on the right side of an > > > > > instantiation. > > > > > > > > > > If I comment out the line .wen (rmw_busy_fifo_wen) it compiles. > > > > > > > > > > > > > > > > > > > > Or if I assign rmw_busy_fifo_wen to a wire and set .wen to the > wire it > > > > > compiles. > > > > > > > > > > > > > > > > > > > > I have several of these in one module and they all fail the same. > > > > > > > > > > > > > > > > > > > > Here are the iverilog errors: > > > > > > > > > > > > > > > > > > > /home/lgliem/macros/carte/cntrlr_if/map_m/llvm_user_obm_bank_if_mapl.v:2066: > > > > > > > > > > error: rmw_busy_fifo_wen Unable to assign to unresolved wires. > > > > > > > > > > > > > > > > > > > /home/lgliem/macros/carte/cntrlr_if/map_m/llvm_user_obm_bank_if_mapl.v:2068: > > > > > > > > > > error: rmw_busy_fifo_wen Unable to assign to unresolved wires. > > > > > > > > > > > > > > > > > > > > Thanks > > > > > > > > > > Lonnie > > > > > > > > > > > > > > > > > > > > reg rmw_busy_fifo_wen; > > > > > > > > > > > > > > > > > > > > always @ (posedge sysclk or posedge user_reset) > > > > > > > > > > if (user_reset) > > > > > > > > > > rmw_busy_fifo_wen <= 1'b0; <----- this is line 2066 > > > > > > > > > > else > > > > > > > > > > rmw_busy_fifo_wen <= ((request_valid_d2 & (set_obm_busy | > > > obm_busy)) > > > > > | <--- this is 2067 > > > > > > > > > > > > > > > (set_normal_wr_patha & (obm_read | obm_read_d1))); > > > > > > > > > > > > > > > > > > > > llvm_mapl_blockram_sync_8x93bit rmw_busy_fifo ( > > > > > > > > > > .out (rmw_busy_fifo_rd[92:00]), > > > > > > > > > > .almost_empty > (rmw_busy_fifo_almost_empty), > > > > > > > > > > .empty (rmw_busy_fifo_empty), > > > > > > > > > > .data_valid (rmw_busy_fifo_valid), > > > > > > > > > > .almost_full (rmw_busy_fifo_full), > > > > > > > > > > .inbit > > > (rmw_busy_fifo_wrdata[92:0]), > > > > > > > > > > .ren (rmw_busy_fifo_ren), > > > > > > > > > > .wen (rmw_busy_fifo_wen), > > > > > > > > > > .ce (1'b1), > > > > > > > > > > .clk (sysclk), > > > > > > > > > > .rst (user_reset) > > > > > > > > > > ); > > > > > > > > > > > > > > > > > > > > > > > > > > > > > ------------------------------------------------------------------------------ > > > > > Site24x7 APM Insight: Get Deep Visibility into Application > Performance > > > > > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month > > > > > Monitor end-to-end web transactions and take corrective actions now > > > > > Troubleshoot faster and improve end-user experience. Signup Now! > > > > > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 > > > > > _______________________________________________ > > > > > Iverilog-devel mailing list > > > > > Ive...@li... > > > > > https://lists.sourceforge.net/lists/listinfo/iverilog-devel > > > > > > > > > > > > > > > > > > > > > ------------------------------------------------------------------------------ > > > > Site24x7 APM Insight: Get Deep Visibility into Application > Performance > > > > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month > > > > Monitor end-to-end web transactions and take corrective actions now > > > > Troubleshoot faster and improve end-user experience. Signup Now! > > > > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 > > > > _______________________________________________ > > > > Iverilog-devel mailing list > > > > Ive...@li... > > > > https://lists.sourceforge.net/lists/listinfo/iverilog-devel > > > > > > > > > > > > > ------------------------------------------------------------------------------ > > > Site24x7 APM Insight: Get Deep Visibility into Application Performance > > > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month > > > Monitor end-to-end web transactions and take corrective actions now > > > Troubleshoot faster and improve end-user experience. Signup Now! > > > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 > > > _______________________________________________ > > > Iverilog-devel mailing list > > > Ive...@li... > > > https://lists.sourceforge.net/lists/listinfo/iverilog-devel > > > > > > > ------------------------------------------------------------------------------ > > Site24x7 APM Insight: Get Deep Visibility into Application Performance > > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month > > Monitor end-to-end web transactions and take corrective actions now > > Troubleshoot faster and improve end-user experience. Signup Now! > > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 > > _______________________________________________ > > Iverilog-devel mailing list > > Ive...@li... > > https://lists.sourceforge.net/lists/listinfo/iverilog-devel > > > > ------------------------------------------------------------------------------ > Site24x7 APM Insight: Get Deep Visibility into Application Performance > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month > Monitor end-to-end web transactions and take corrective actions now > Troubleshoot faster and improve end-user experience. Signup Now! > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 > _______________________________________________ > Iverilog-devel mailing list > Ive...@li... > https://lists.sourceforge.net/lists/listinfo/iverilog-devel > |
|
From: Cary R. <cy...@ya...> - 2016-01-13 15:55:10
|
I agree with the rest, this sure look like you are assigning to a register which is supported in SystemVerilog, but is not currently supported in Icarus.
A working example would certainly help.
Cary
On Tuesday, January 12, 2016 12:49 PM, Iztok Jeras <izt...@gm...> wrote:
you should further check if both 'ce' and 'wren' ports are inputs, and that the signals are not driven inside those modules
On Tue, Jan 12, 2016 at 9:18 PM, Lonnie Gliem <lg...@sr...> wrote:
Not much on the grep I don't see any continuous assignments.
$ grep wen
/temp/builds/150918-0934/carte/macros/carte/cntrlr_if/map_m/llvm_mapl_blockram_sync_8x93bit.v
input wen,
.ce (wen)
.wren (wen),
Lonnie
On Tue, Jan 12, 2016 at 08:54:29PM +0100, Iztok Jeras wrote:
> for now could jou just grep all lines containing wen
> inside llvm_mapl_blockram_sync_8x93bit
>
> $ grep wen llvm_mapl_blockram_sync_8x93bit.v
>
> On Tue, Jan 12, 2016 at 7:47 PM, Lonnie Gliem <lg...@sr...>
> wrote:
>
> > It is an input.
> >
> > module llvm_mapl_blockram_sync_8x93bit (
> > output wire [92:0] out,
> > output reg almost_empty,
> > output reg empty,
> > output reg data_valid,
> > output reg almost_full,
> > input [92:0] inbit,
> > input ren,
> > input wen,
> > input ce,
> > input clk,
> > input rst
> > );
> >
> > I will try and cut it down to s small testcase but it may take a bit it
> > is quite large.
> >
> > Lonnie
> >
> > On Tue, Jan 12, 2016 at 07:20:59PM +0100, Iztok Jeras wrote:
> > > Hi,
> > >
> > > Could you check the direction of the 'wen' port inside the
> > > module llvm_mapl_blockram_sync_8x93bit? And perhaps if there are any
> > > asignments to the wen signal inside the module.
> > >
> > > Some simulators ignore signal directions, but check for multiple drivers.
> > > So although the direction is wrong, the design might be functionally
> > > correct.
> > >
> > > Regards,
> > > Iztok Jeras
> > >
> > > On Tue, Jan 12, 2016 at 6:10 PM, Lonnie L Gliem <lg...@sr...
> > >
> > > wrote:
> > >
> > > > I ran into some verilog code that iverilog is failing to compile but
> > vcs
> > > >
> > > > does.
> > > >
> > > >
> > > >
> > > > It appears the problem is having the reg on the right side of an
> > > > instantiation.
> > > >
> > > > If I comment out the line .wen (rmw_busy_fifo_wen) it compiles.
> > > >
> > > >
> > > >
> > > > Or if I assign rmw_busy_fifo_wen to a wire and set .wen to the wire it
> > > > compiles.
> > > >
> > > >
> > > >
> > > > I have several of these in one module and they all fail the same.
> > > >
> > > >
> > > >
> > > > Here are the iverilog errors:
> > > >
> > > >
> > > >
> > /home/lgliem/macros/carte/cntrlr_if/map_m/llvm_user_obm_bank_if_mapl.v:2066:
> > > >
> > > > error: rmw_busy_fifo_wen Unable to assign to unresolved wires.
> > > >
> > > >
> > > >
> > /home/lgliem/macros/carte/cntrlr_if/map_m/llvm_user_obm_bank_if_mapl.v:2068:
> > > >
> > > > error: rmw_busy_fifo_wen Unable to assign to unresolved wires.
> > > >
> > > >
> > > >
> > > > Thanks
> > > >
> > > > Lonnie
> > > >
> > > >
> > > >
> > > > reg rmw_busy_fifo_wen;
> > > >
> > > >
> > > >
> > > > always @ (posedge sysclk or posedge user_reset)
> > > >
> > > > if (user_reset)
> > > >
> > > > rmw_busy_fifo_wen <= 1'b0; <----- this is line 2066
> > > >
> > > > else
> > > >
> > > > rmw_busy_fifo_wen <= ((request_valid_d2 & (set_obm_busy |
> > obm_busy))
> > > > | <--- this is 2067
> > > >
> > > >
> > > > (set_normal_wr_patha & (obm_read | obm_read_d1)));
> > > >
> > > >
> > > >
> > > > llvm_mapl_blockram_sync_8x93bit rmw_busy_fifo (
> > > >
> > > > .out (rmw_busy_fifo_rd[92:00]),
> > > >
> > > > .almost_empty (rmw_busy_fifo_almost_empty),
> > > >
> > > > .empty (rmw_busy_fifo_empty),
> > > >
> > > > .data_valid (rmw_busy_fifo_valid),
> > > >
> > > > .almost_full (rmw_busy_fifo_full),
> > > >
> > > > .inbit
> > (rmw_busy_fifo_wrdata[92:0]),
> > > >
> > > > .ren (rmw_busy_fifo_ren),
> > > >
> > > > .wen (rmw_busy_fifo_wen),
> > > >
> > > > .ce (1'b1),
> > > >
> > > > .clk (sysclk),
> > > >
> > > > .rst (user_reset)
> > > >
> > > > );
> > > >
> > > >
> > > >
> > > >
> > > >
> > ------------------------------------------------------------------------------
> > > > Site24x7 APM Insight: Get Deep Visibility into Application Performance
> > > > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
> > > > Monitor end-to-end web transactions and take corrective actions now
> > > > Troubleshoot faster and improve end-user experience. Signup Now!
> > > > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140
> > > > _______________________________________________
> > > > Iverilog-devel mailing list
> > > > Ive...@li...
> > > > https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> > > >
> > > >
> >
> > >
> > ------------------------------------------------------------------------------
> > > Site24x7 APM Insight: Get Deep Visibility into Application Performance
> > > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
> > > Monitor end-to-end web transactions and take corrective actions now
> > > Troubleshoot faster and improve end-user experience. Signup Now!
> > > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140
> > > _______________________________________________
> > > Iverilog-devel mailing list
> > > Ive...@li...
> > > https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> >
> >
> >
> > ------------------------------------------------------------------------------
> > Site24x7 APM Insight: Get Deep Visibility into Application Performance
> > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
> > Monitor end-to-end web transactions and take corrective actions now
> > Troubleshoot faster and improve end-user experience. Signup Now!
> > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140
> > _______________________________________________
> > Iverilog-devel mailing list
> > Ive...@li...
> > https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> >
> ------------------------------------------------------------------------------
> Site24x7 APM Insight: Get Deep Visibility into Application Performance
> APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
> Monitor end-to-end web transactions and take corrective actions now
> Troubleshoot faster and improve end-user experience. Signup Now!
> http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140
> _______________________________________________
> Iverilog-devel mailing list
> Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
------------------------------------------------------------------------------
Site24x7 APM Insight: Get Deep Visibility into Application Performance
APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
Monitor end-to-end web transactions and take corrective actions now
Troubleshoot faster and improve end-user experience. Signup Now!
http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140
_______________________________________________
Iverilog-devel mailing list
Ive...@li...
https://lists.sourceforge.net/lists/listinfo/iverilog-devel
------------------------------------------------------------------------------
Site24x7 APM Insight: Get Deep Visibility into Application Performance
APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
Monitor end-to-end web transactions and take corrective actions now
Troubleshoot faster and improve end-user experience. Signup Now!
http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140
_______________________________________________
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|
|
From: Lonnie G. <lg...@sr...> - 2016-01-13 16:00:37
|
I have an example ready just have to get Managements approval to send it. On Wed, Jan 13, 2016 at 03:52:19PM +0000, Cary R. wrote: > I agree with the rest, this sure look like you are assigning to a register which is supported in SystemVerilog, but is not currently supported in Icarus. > > A working example would certainly help. > Cary > > On Tuesday, January 12, 2016 12:49 PM, Iztok Jeras <izt...@gm...> wrote: > > > you should further check if both 'ce' and 'wren' ports are inputs, and that the signals are not driven inside those modules > On Tue, Jan 12, 2016 at 9:18 PM, Lonnie Gliem <lg...@sr...> wrote: > > Not much on the grep I don't see any continuous assignments. > > $ grep wen > /temp/builds/150918-0934/carte/macros/carte/cntrlr_if/map_m/llvm_mapl_blockram_sync_8x93bit.v > input wen, > .ce (wen) > .wren (wen), > > Lonnie > > On Tue, Jan 12, 2016 at 08:54:29PM +0100, Iztok Jeras wrote: > > for now could jou just grep all lines containing wen > > inside llvm_mapl_blockram_sync_8x93bit > > > > $ grep wen llvm_mapl_blockram_sync_8x93bit.v > > > > On Tue, Jan 12, 2016 at 7:47 PM, Lonnie Gliem <lg...@sr...> > > wrote: > > > > > It is an input. > > > > > > module llvm_mapl_blockram_sync_8x93bit ( > > > output wire [92:0] out, > > > output reg almost_empty, > > > output reg empty, > > > output reg data_valid, > > > output reg almost_full, > > > input [92:0] inbit, > > > input ren, > > > input wen, > > > input ce, > > > input clk, > > > input rst > > > ); > > > > > > I will try and cut it down to s small testcase but it may take a bit it > > > is quite large. > > > > > > Lonnie > > > > > > On Tue, Jan 12, 2016 at 07:20:59PM +0100, Iztok Jeras wrote: > > > > Hi, > > > > > > > > Could you check the direction of the 'wen' port inside the > > > > module llvm_mapl_blockram_sync_8x93bit? And perhaps if there are any > > > > asignments to the wen signal inside the module. > > > > > > > > Some simulators ignore signal directions, but check for multiple drivers. > > > > So although the direction is wrong, the design might be functionally > > > > correct. > > > > > > > > Regards, > > > > Iztok Jeras > > > > > > > > On Tue, Jan 12, 2016 at 6:10 PM, Lonnie L Gliem <lg...@sr... > > > > > > > > wrote: > > > > > > > > > I ran into some verilog code that iverilog is failing to compile but > > > vcs > > > > > > > > > > does. > > > > > > > > > > > > > > > > > > > > It appears the problem is having the reg on the right side of an > > > > > instantiation. > > > > > > > > > > If I comment out the line .wen (rmw_busy_fifo_wen) it compiles. > > > > > > > > > > > > > > > > > > > > Or if I assign rmw_busy_fifo_wen to a wire and set .wen to the wire it > > > > > compiles. > > > > > > > > > > > > > > > > > > > > I have several of these in one module and they all fail the same. > > > > > > > > > > > > > > > > > > > > Here are the iverilog errors: > > > > > > > > > > > > > > > > > > /home/lgliem/macros/carte/cntrlr_if/map_m/llvm_user_obm_bank_if_mapl.v:2066: > > > > > > > > > > error: rmw_busy_fifo_wen Unable to assign to unresolved wires. > > > > > > > > > > > > > > > > > > /home/lgliem/macros/carte/cntrlr_if/map_m/llvm_user_obm_bank_if_mapl.v:2068: > > > > > > > > > > error: rmw_busy_fifo_wen Unable to assign to unresolved wires. > > > > > > > > > > > > > > > > > > > > Thanks > > > > > > > > > > Lonnie > > > > > > > > > > > > > > > > > > > > reg rmw_busy_fifo_wen; > > > > > > > > > > > > > > > > > > > > always @ (posedge sysclk or posedge user_reset) > > > > > > > > > > if (user_reset) > > > > > > > > > > rmw_busy_fifo_wen <= 1'b0; <----- this is line 2066 > > > > > > > > > > else > > > > > > > > > > rmw_busy_fifo_wen <= ((request_valid_d2 & (set_obm_busy | > > > obm_busy)) > > > > > | <--- this is 2067 > > > > > > > > > > > > > > > (set_normal_wr_patha & (obm_read | obm_read_d1))); > > > > > > > > > > > > > > > > > > > > llvm_mapl_blockram_sync_8x93bit rmw_busy_fifo ( > > > > > > > > > > .out (rmw_busy_fifo_rd[92:00]), > > > > > > > > > > .almost_empty (rmw_busy_fifo_almost_empty), > > > > > > > > > > .empty (rmw_busy_fifo_empty), > > > > > > > > > > .data_valid (rmw_busy_fifo_valid), > > > > > > > > > > .almost_full (rmw_busy_fifo_full), > > > > > > > > > > .inbit > > > (rmw_busy_fifo_wrdata[92:0]), > > > > > > > > > > .ren (rmw_busy_fifo_ren), > > > > > > > > > > .wen (rmw_busy_fifo_wen), > > > > > > > > > > .ce (1'b1), > > > > > > > > > > .clk (sysclk), > > > > > > > > > > .rst (user_reset) > > > > > > > > > > ); > > > > > > > > > > > > > > > > > > > > > > > > > > > > ------------------------------------------------------------------------------ > > > > > Site24x7 APM Insight: Get Deep Visibility into Application Performance > > > > > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month > > > > > Monitor end-to-end web transactions and take corrective actions now > > > > > Troubleshoot faster and improve end-user experience. Signup Now! > > > > > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 > > > > > _______________________________________________ > > > > > Iverilog-devel mailing list > > > > > Ive...@li... > > > > > https://lists.sourceforge.net/lists/listinfo/iverilog-devel > > > > > > > > > > > > > > > > > > > > ------------------------------------------------------------------------------ > > > > Site24x7 APM Insight: Get Deep Visibility into Application Performance > > > > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month > > > > Monitor end-to-end web transactions and take corrective actions now > > > > Troubleshoot faster and improve end-user experience. Signup Now! > > > > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 > > > > _______________________________________________ > > > > Iverilog-devel mailing list > > > > Ive...@li... > > > > https://lists.sourceforge.net/lists/listinfo/iverilog-devel > > > > > > > > > > > > ------------------------------------------------------------------------------ > > > Site24x7 APM Insight: Get Deep Visibility into Application Performance > > > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month > > > Monitor end-to-end web transactions and take corrective actions now > > > Troubleshoot faster and improve end-user experience. Signup Now! > > > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 > > > _______________________________________________ > > > Iverilog-devel mailing list > > > Ive...@li... > > > https://lists.sourceforge.net/lists/listinfo/iverilog-devel > > > > > > ------------------------------------------------------------------------------ > > Site24x7 APM Insight: Get Deep Visibility into Application Performance > > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month > > Monitor end-to-end web transactions and take corrective actions now > > Troubleshoot faster and improve end-user experience. Signup Now! > > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 > > _______________________________________________ > > Iverilog-devel mailing list > > Ive...@li... > > https://lists.sourceforge.net/lists/listinfo/iverilog-devel > > > ------------------------------------------------------------------------------ > Site24x7 APM Insight: Get Deep Visibility into Application Performance > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month > Monitor end-to-end web transactions and take corrective actions now > Troubleshoot faster and improve end-user experience. Signup Now! > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 > _______________________________________________ > Iverilog-devel mailing list > Ive...@li... > https://lists.sourceforge.net/lists/listinfo/iverilog-devel > > > > ------------------------------------------------------------------------------ > Site24x7 APM Insight: Get Deep Visibility into Application Performance > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month > Monitor end-to-end web transactions and take corrective actions now > Troubleshoot faster and improve end-user experience. Signup Now! > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 > _______________________________________________ > Iverilog-devel mailing list > Ive...@li... > https://lists.sourceforge.net/lists/listinfo/iverilog-devel > > > ------------------------------------------------------------------------------ > Site24x7 APM Insight: Get Deep Visibility into Application Performance > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month > Monitor end-to-end web transactions and take corrective actions now > Troubleshoot faster and improve end-user experience. Signup Now! > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 > _______________________________________________ > Iverilog-devel mailing list > Ive...@li... > https://lists.sourceforge.net/lists/listinfo/iverilog-devel |
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