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From: Larry D. <ldo...@re...> - 2015-08-20 15:53:44
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Friends -
Open ended question -- what should a stable v10 say and do when
given the "-S" option?
Right now it starts with
Warning: Synthesis is not currently being maintained and may not
function correctly. V0.8 was the last release branch to
have active synthesis development and support!
I venture to say that the synthesis pass in v10 is not useful for targeting
real hardware, but the transformations can be interesting for understanding
the abstract synthesizability of Verilog code.
I can trigger a handful of asserts in Icarus' synth pass by trying
to synthesize my typical Verilog. That doesn't seem like a show-stopper
for v10, but it does suggest that a warning similar to what we have now
is still called for. Specifically:
assert: /home/ldoolitt/git/iverilog/synth2.cc:182: failed assertion 0
assert: /home/ldoolitt/git/iverilog/synth2.cc:232: failed assertion nex_out.pin_count()==1
internal error: NetCondit::synth_async: Mux input sizes do not match. A size=32, B size=17
Should I turn in bug reports?
One change in the larger picture since v0.8 in 2004 is the
emergence of yosys[1], which is open source and _can_ actually
synthesize for real hardware. I'd also observe that yosys
would have a really hard time going public _without_ quality
simulations from Icarus; it has an extensive self-test process
based on using Icarus to compare the input Verilog with exported
post-synthesis structural Verilog.
- Larry
[1] http://www.clifford.at/yosys/
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From: Guy H. <ghu...@gm...> - 2015-08-20 19:24:38
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Hi Larry, Have you looked at the sizer target? This is something which does more abstract analysis of the device without creating full results. Guy On Thursday, August 20, 2015, Larry Doolittle <ldo...@re...> wrote: > Friends - > > Open ended question -- what should a stable v10 say and do when > given the "-S" option? > > Right now it starts with > Warning: Synthesis is not currently being maintained and may not > function correctly. V0.8 was the last release branch to > have active synthesis development and support! > > I venture to say that the synthesis pass in v10 is not useful for targeting > real hardware, but the transformations can be interesting for understanding > the abstract synthesizability of Verilog code. > > I can trigger a handful of asserts in Icarus' synth pass by trying > to synthesize my typical Verilog. That doesn't seem like a show-stopper > for v10, but it does suggest that a warning similar to what we have now > is still called for. Specifically: > assert: /home/ldoolitt/git/iverilog/synth2.cc:182: failed assertion 0 > assert: /home/ldoolitt/git/iverilog/synth2.cc:232: failed assertion > nex_out.pin_count()==1 > internal error: NetCondit::synth_async: Mux input sizes do not match. A > size=32, B size=17 > Should I turn in bug reports? > > One change in the larger picture since v0.8 in 2004 is the > emergence of yosys[1], which is open source and _can_ actually > synthesize for real hardware. I'd also observe that yosys > would have a really hard time going public _without_ quality > simulations from Icarus; it has an extensive self-test process > based on using Icarus to compare the input Verilog with exported > post-synthesis structural Verilog. > > - Larry > > [1] http://www.clifford.at/yosys/ > > > ------------------------------------------------------------------------------ > _______________________________________________ > Iverilog-devel mailing list > Ive...@li... <javascript:;> > https://lists.sourceforge.net/lists/listinfo/iverilog-devel > |
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From: Stephen W. <st...@ic...> - 2015-08-20 19:27:32
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-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Well, the synthesis is not awesome in v10, but it may actually be better than v0.8, so we may want to kill that warning. We have a couple of targets now that actually use synthesis. (See the blif and sizer targets.) On 08/20/2015 08:53 AM, Larry Doolittle wrote: > Friends - > > Open ended question -- what should a stable v10 say and do when > given the "-S" option? > > Right now it starts with Warning: Synthesis is not currently being > maintained and may not function correctly. V0.8 was the last > release branch to have active synthesis development and support! > > I venture to say that the synthesis pass in v10 is not useful for > targeting real hardware, but the transformations can be interesting > for understanding the abstract synthesizability of Verilog code. - -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep." -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iEYEARECAAYFAlXWKhoACgkQrPt1Sc2b3imwRACfazTlrJejmP0wNuCCn9HHPCVJ HmIAoIIxp9wHeea0Md1+EAq5KuyKLK8a =RUg5 -----END PGP SIGNATURE----- |
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From: Larry D. <ldo...@re...> - 2015-08-20 20:37:58
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Steve - On Thu, Aug 20, 2015 at 12:27:22PM -0700, Stephen Williams wrote: > Well, the synthesis is not awesome in v10, but it may actually > be better than v0.8, so we may want to kill that warning. We have > a couple of targets now that actually use synthesis. (See the blif > and sizer targets.) OK then. See bug #993: assertion in synth. And I think I can come up with a couple more. - Larry |
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From: Martin W. <mai...@ma...> - 2015-08-20 21:05:04
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Stephen Williams wrote: > Well, the synthesis is not awesome in v10, but it may actually > be better than v0.8, so we may want to kill that warning. We have > a couple of targets now that actually use synthesis. (See the blif > and sizer targets.) Also one of our users has created a target for Atmel PLDs. There's still quite a long list of synthesis tests that no longer work though - see regress-v11/list - so maybe a warning that synthesis support is incomplete is still in order. Martin |
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From: Stephen W. <st...@ic...> - 2015-08-20 21:11:46
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-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Sure. It remains true that high-level synthesis is a low priority so some sort of message to communicate that makes sense, but we certainly do NOT want to be sending users to v0.8, or even v0.9. There are some synthesis based targets, so we do want to support limited synthesis, we just don't want to over-promise. On 08/20/2015 02:04 PM, Martin Whitaker wrote: > Stephen Williams wrote: >> Well, the synthesis is not awesome in v10, but it may actually be >> better than v0.8, so we may want to kill that warning. We have a >> couple of targets now that actually use synthesis. (See the blif >> and sizer targets.) > > Also one of our users has created a target for Atmel PLDs. > > There's still quite a long list of synthesis tests that no longer > work though - see regress-v11/list - so maybe a warning that > synthesis support is incomplete is still in order. - -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep." -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iEYEARECAAYFAlXWQogACgkQrPt1Sc2b3ilj3gCfW161sIqr4ZrUQ5etgMffs2jj VS0AoNievG+gBbsox1C6hojg+af39JGK =XHjy -----END PGP SIGNATURE----- |
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From: Larry D. <ldo...@re...> - 2015-08-20 21:19:34
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Martin - On Thu, Aug 20, 2015 at 10:04:52PM +0100, Martin Whitaker wrote: > There's still quite a long list of synthesis tests that no longer work though > - see regress-v11/list After five minutes of rummaging around on https://sourceforge.net/projects/ivtest/ I couldn't figure out the git access magic. Is sourceforge being deliberately opaque, or did something break? I got the six-month-old ivtest_v1.0.tar.gz, but of course there's no mention of v10 or v11 in there. > - so maybe a warning that synthesis support is > incomplete is still in order. Sure, I'm OK with that. I agree with Steve that mentioning v0.8 is probably a mistake. - Larry |
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From: Martin W. <mai...@ma...> - 2015-08-20 21:29:00
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Larry, Larry Doolittle wrote: > After five minutes of rummaging around on > https://sourceforge.net/projects/ivtest/ > I couldn't figure out the git access magic. > Is sourceforge being deliberately opaque, or did something break? > I got the six-month-old ivtest_v1.0.tar.gz, but of course > there's no mention of v10 or v11 in there. > We moved to GitHub a while back: https://github.com/steveicarus/ivtest >> - so maybe a warning that synthesis support is >> incomplete is still in order. > > Sure, I'm OK with that. I agree with Steve that mentioning > v0.8 is probably a mistake. > Likewise. Martin |
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From: Larry D. <ldo...@re...> - 2015-08-20 21:43:35
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Steve - On Thu, Aug 20, 2015 at 10:28:52PM +0100, Martin Whitaker wrote: > Larry Doolittle wrote: > > After five minutes of rummaging around on > > https://sourceforge.net/projects/ivtest/ > > I couldn't figure out the git access magic. > We moved to GitHub a while back: > https://github.com/steveicarus/ivtest Ah. Much better. Steve, I guess you should update http://iverilog.icarus.com/ that still points people to sourceforge. - Larry |
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From: Stephen W. <st...@ic...> - 2015-08-20 21:51:34
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-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 On 08/20/2015 02:43 PM, Larry Doolittle wrote: > Steve, I guess you should update http://iverilog.icarus.com/ that > still points people to sourceforge. > Done, thanks. - -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep." -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iEYEARECAAYFAlXWS9sACgkQrPt1Sc2b3imXZQCfZRg1kWxZsnIVvlYAq+IMlMd3 FKAAn0FaxeBMlkt9pi/LiyiIh+HF2eIT =H9RW -----END PGP SIGNATURE----- |
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