Menu
▾
▴
iverilog-devel
|
From: Lonnie G. <lg...@sr...> - 2015-01-08 21:16:43
|
What is the do while syntax for iverilog. I have the loop below that compiles fine in vcs but errors out in iverilog. do begin @(posedge clk); err = $carte_accept(listening_sockfd); end while (err == -1); Here are the errors. /home/dvl/installs/TRIAL_5.3_64/opt/srcci/comp/lib/macros/map_m/v/eth_command_accept.v:87: syntax error /home/dvl/installs/TRIAL_5.3_64/opt/srcci/comp/lib/macros/map_m/v/eth_command_accept.v:88: error: malformed statement /home/dvl/installs/TRIAL_5.3_64/opt/srcci/comp/lib/macros/map_m/v/eth_command_accept.v:95: syntax error Here is the version: Icarus Verilog version 0.10.0 (devel) (s20140801-15-g4ea512c) Thansk for the help Lonnie |
|
From: Cary R. <cy...@ya...> - 2015-01-08 21:37:05
|
Are you telling Icarus to use SystemVerilog (e.g. -g2009, -g2012 or -g2005-sv)? The following example runs correctly (displays 0 to 9) using the latest code from git and the -g2009 flag:
module top;
integer val;
initial begin
val = 0;
do begin
$display(val);
val += 1;
end while (val < 10);
end
endmodule
Since SystemVerilog is not that complete in Icarus it is not enabled by default.
Cary
On Thursday, January 8, 2015 1:17 PM, Lonnie Gliem <lg...@sr...> wrote:
What is the do while syntax for iverilog. I have the loop below that
compiles fine in vcs but errors out in iverilog.
do begin
@(posedge clk);
err = $carte_accept(listening_sockfd);
end while (err == -1);
Here are the errors.
/home/dvl/installs/TRIAL_5.3_64/opt/srcci/comp/lib/macros/map_m/v/eth_command_accept.v:87:
syntax error
/home/dvl/installs/TRIAL_5.3_64/opt/srcci/comp/lib/macros/map_m/v/eth_command_accept.v:88:
error: malformed statement
/home/dvl/installs/TRIAL_5.3_64/opt/srcci/comp/lib/macros/map_m/v/eth_command_accept.v:95:
syntax error
Here is the version:
Icarus Verilog version 0.10.0 (devel) (s20140801-15-g4ea512c)
Thansk for the help
Lonnie
------------------------------------------------------------------------------
Dive into the World of Parallel Programming! The Go Parallel Website,
sponsored by Intel and developed in partnership with Slashdot Media, is your
hub for all things parallel software development, from weekly thought
leadership blogs to news, videos, case studies, tutorials and more. Take a
look and join the conversation now. http://goparallel.sourceforge.net
_______________________________________________
Iverilog-devel mailing list
Ive...@li...
https://lists.sourceforge.net/lists/listinfo/iverilog-devel
|
|
From: Lonnie L G. <lg...@sr...> - 2015-01-08 21:46:15
|
I wasn’t specifying a –g I added –g2009 and it works.
Thanks
Lonnie
From: Cary R. [mailto:cy...@ya...]
Sent: Thursday, January 08, 2015 3:37 PM
To: Discussions concerning Icarus Verilog development
Subject: Re: [Iverilog-devel] do while loop syntax.
Are you telling Icarus to use SystemVerilog (e.g. -g2009, -g2012 or -g2005-sv)? The following example runs correctly (displays 0 to 9) using the latest code from git and the -g2009 flag:
module top;
integer val;
initial begin
val = 0;
do begin
$display(val);
val += 1;
end while (val < 10);
end
endmodule
Since SystemVerilog is not that complete in Icarus it is not enabled by default.
Cary
On Thursday, January 8, 2015 1:17 PM, Lonnie Gliem <lg...@sr...> wrote:
What is the do while syntax for iverilog. I have the loop below that
compiles fine in vcs but errors out in iverilog.
do begin
@(posedge clk);
err = $carte_accept(listening_sockfd);
end while (err == -1);
Here are the errors.
/home/dvl/installs/TRIAL_5.3_64/opt/srcci/comp/lib/macros/map_m/v/eth_command_accept.v:87:
syntax error
/home/dvl/installs/TRIAL_5.3_64/opt/srcci/comp/lib/macros/map_m/v/eth_command_accept.v:88:
error: malformed statement
/home/dvl/installs/TRIAL_5.3_64/opt/srcci/comp/lib/macros/map_m/v/eth_command_accept.v:95:
syntax error
Here is the version:
Icarus Verilog version 0.10.0 (devel) (s20140801-15-g4ea512c)
Thansk for the help
Lonnie
------------------------------------------------------------------------------
Dive into the World of Parallel Programming! The Go Parallel Website,
sponsored by Intel and developed in partnership with Slashdot Media, is your
hub for all things parallel software development, from weekly thought
leadership blogs to news, videos, case studies, tutorials and more. Take a
look and join the conversation now. http://goparallel.sourceforge.net <http://goparallel.sourceforge.net/>
_______________________________________________
Iverilog-devel mailing list
Ive...@li...
https://lists.sourceforge.net/lists/listinfo/iverilog-devel
|
|
From: Lonnie L G. <lg...@sr...> - 2015-01-09 20:58:52
|
What is the earliest version of iverilog that has –g2009 support I tried it with .9.6 on centos and it only has g2005? Is that the latest version on centos? That’s what I see on centos 6.5.
Lonnie
From: Cary R. [mailto:cy...@ya...]
Sent: Thursday, January 08, 2015 3:37 PM
To: Discussions concerning Icarus Verilog development
Subject: Re: [Iverilog-devel] do while loop syntax.
Are you telling Icarus to use SystemVerilog (e.g. -g2009, -g2012 or -g2005-sv)? The following example runs correctly (displays 0 to 9) using the latest code from git and the -g2009 flag:
module top;
integer val;
initial begin
val = 0;
do begin
$display(val);
val += 1;
end while (val < 10);
end
endmodule
Since SystemVerilog is not that complete in Icarus it is not enabled by default.
Cary
On Thursday, January 8, 2015 1:17 PM, Lonnie Gliem <lg...@sr...> wrote:
What is the do while syntax for iverilog. I have the loop below that
compiles fine in vcs but errors out in iverilog.
do begin
@(posedge clk);
err = $carte_accept(listening_sockfd);
end while (err == -1);
Here are the errors.
/home/dvl/installs/TRIAL_5.3_64/opt/srcci/comp/lib/macros/map_m/v/eth_command_accept.v:87:
syntax error
/home/dvl/installs/TRIAL_5.3_64/opt/srcci/comp/lib/macros/map_m/v/eth_command_accept.v:88:
error: malformed statement
/home/dvl/installs/TRIAL_5.3_64/opt/srcci/comp/lib/macros/map_m/v/eth_command_accept.v:95:
syntax error
Here is the version:
Icarus Verilog version 0.10.0 (devel) (s20140801-15-g4ea512c)
Thansk for the help
Lonnie
------------------------------------------------------------------------------
Dive into the World of Parallel Programming! The Go Parallel Website,
sponsored by Intel and developed in partnership with Slashdot Media, is your
hub for all things parallel software development, from weekly thought
leadership blogs to news, videos, case studies, tutorials and more. Take a
look and join the conversation now. http://goparallel.sourceforge.net <http://goparallel.sourceforge.net/>
_______________________________________________
Iverilog-devel mailing list
Ive...@li...
https://lists.sourceforge.net/lists/listinfo/iverilog-devel
|
|
From: Cary R. <cy...@ya...> - 2015-01-09 23:41:28
|
We started adding parts of SystemVerilog in V0.10 (development from git or snapshots). It is fairly trivial to compile Icarus from source. Instructions are here: Installation Guide | | | | | | | | | | | Installation GuideIcarus may be installed from source code or from pre-packaged binary distributions. Icarus is developed for Unix-like environments but can also be comp... | | | | View on iverilog.wikia.com | Preview by Yahoo | | | | | On Friday, January 9, 2015 12:57 PM, Lonnie L Gliem <lg...@sr...> wrote: #yiv1803080946 #yiv1803080946 -- _filtered #yiv1803080946 {font-family:Helvetica;panose-1:2 11 6 4 2 2 2 2 2 4;} _filtered #yiv1803080946 {font-family:Helvetica;panose-1:2 11 6 4 2 2 2 2 2 4;} _filtered #yiv1803080946 {font-family:Calibri;panose-1:2 15 5 2 2 2 4 3 2 4;} _filtered #yiv1803080946 {font-family:Tahoma;panose-1:2 11 6 4 3 5 4 4 2 4;}#yiv1803080946 #yiv1803080946 p.yiv1803080946MsoNormal, #yiv1803080946 li.yiv1803080946MsoNormal, #yiv1803080946 div.yiv1803080946MsoNormal {margin:0in;margin-bottom:.0001pt;font-size:12.0pt;}#yiv1803080946 a:link, #yiv1803080946 span.yiv1803080946MsoHyperlink {color:blue;text-decoration:underline;}#yiv1803080946 a:visited, #yiv1803080946 span.yiv1803080946MsoHyperlinkFollowed {color:purple;text-decoration:underline;}#yiv1803080946 span.yiv1803080946EmailStyle17 {color:#1F497D;}#yiv1803080946 .yiv1803080946MsoChpDefault {font-size:10.0pt;} _filtered #yiv1803080946 {margin:1.0in 1.0in 1.0in 1.0in;}#yiv1803080946 div.yiv1803080946WordSection1 {}#yiv1803080946 What is the earliest version of iverilog that has –g2009 support I tried it with .9.6 on centos and it only has g2005? Is that the latest version on centos? That’s what I see on centos 6.5. Lonnie From: Cary R. [mailto:cy...@ya...] Sent: Thursday, January 08, 2015 3:37 PM To: Discussions concerning Icarus Verilog development Subject: Re: [Iverilog-devel] do while loop syntax. Are you telling Icarus to use SystemVerilog (e.g. -g2009, -g2012 or -g2005-sv)? The following example runs correctly (displays 0 to 9) using the latest code from git and the -g2009 flag: module top; integer val; initial begin val = 0; do begin $display(val); val += 1; end while (val < 10); end endmodule Since SystemVerilog is not that complete in Icarus it is not enabled by default. Cary On Thursday, January 8, 2015 1:17 PM, Lonnie Gliem <lg...@sr...> wrote: What is the do while syntax for iverilog. I have the loop below that compiles fine in vcs but errors out in iverilog. do begin @(posedge clk); err = $carte_accept(listening_sockfd); end while (err == -1); Here are the errors. /home/dvl/installs/TRIAL_5.3_64/opt/srcci/comp/lib/macros/map_m/v/eth_command_accept.v:87: syntax error /home/dvl/installs/TRIAL_5.3_64/opt/srcci/comp/lib/macros/map_m/v/eth_command_accept.v:88: error: malformed statement /home/dvl/installs/TRIAL_5.3_64/opt/srcci/comp/lib/macros/map_m/v/eth_command_accept.v:95: syntax error Here is the version: Icarus Verilog version 0.10.0 (devel) (s20140801-15-g4ea512c) Thansk for the help Lonnie ------------------------------------------------------------------------------ Dive into the World of Parallel Programming! The Go Parallel Website, sponsored by Intel and developed in partnership with Slashdot Media, is your hub for all things parallel software development, from weekly thought leadership blogs to news, videos, case studies, tutorials and more. Take a look and join the conversation now. http://goparallel.sourceforge.net _______________________________________________ Iverilog-devel mailing list Ive...@li... https://lists.sourceforge.net/lists/listinfo/iverilog-devel |
×
Want the latest updates on software, tech news, and AI?
Get latest updates about software, tech news, and AI from SourceForge directly in your inbox once a month.
Thanks for helping keep SourceForge clean.
X