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From: Dan M. <dan...@gm...> - 2016-02-08 20:50:07
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I am using iverilog to learn SystemVerilog. I am following along in a
digital system design book and am having trouble building one of the
examples. The code uses a function to calculate log2:
module #(parameter AL = 8, BL = 8, QL = AL + BL) ...
logic[clog2(AL):0] count;
...
function clog2(input int n);
begin
clog2 = 0;
n--;
while(n > 0)
begin
clog2++;
n >>= 1;
end
end
endfunction
endmodule
I calling iverilog like this:
iverilog -g2012 -Wall -o booth booth.sv
It seems to get hung processing the loop or detecting n == 0 or
something. Is there an easy way
to debug this? I was thinking I'd run iverilog within gdb but maybe
there is a faster way to determine what is happening?
Regards,
Dan McLeran
|
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From: Stephen W. <st...@ic...> - 2016-02-09 00:13:56
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If you make a small but complete example that we cal compile for ourselves, we can take a look at this. On 02/08/2016 12:50 PM, Dan McLeran wrote: > I am using iverilog to learn SystemVerilog. I am following along in a > digital system design book and am having trouble building one of the > examples. The code uses a function to calculate log2: > > module #(parameter AL = 8, BL = 8, QL = AL + BL) ... > > logic[clog2(AL):0] count; > ... > function clog2(input int n); > begin > clog2 = 0; > n--; > while(n > 0) > begin > clog2++; > n >>= 1; > end > end > endfunction > endmodule > > I calling iverilog like this: > > iverilog -g2012 -Wall -o booth booth.sv > > It seems to get hung processing the loop or detecting n == 0 or > something. Is there an easy way > to debug this? I was thinking I'd run iverilog within gdb but maybe > there is a faster way to determine what is happening? > > Regards, > > Dan McLeran > > ------------------------------------------------------------------------------ > Site24x7 APM Insight: Get Deep Visibility into Application Performance > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month > Monitor end-to-end web transactions and take corrective actions now > Troubleshoot faster and improve end-user experience. Signup Now! > http://pubads.g.doubleclick.net/gampad/clk?id=272487151&iu=/4140 > _______________________________________________ > Iverilog-devel mailing list > Ive...@li... > https://lists.sourceforge.net/lists/listinfo/iverilog-devel > -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep." |
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From: Dan M. <dan...@gm...> - 2016-02-09 04:02:04
|
Thanks. Here is a simple example. Using the function clog2 in the
declaration of the logic array causes the failure. Using clog2 in the
sequential logic appears to work.
iverilog -g2012 -Wall -o example example.sv
//example.sv
module example #(parameter N = 8) (output logic[3:0] result, input logic clk);
//logic[clog2(N):0] temp; //comment this line back in to see the failure
always@(posedge clk)
result <= clog2(N);
function int clog2(input int n);
begin
clog2 = 0;
n--;
while(n > 0)
begin
clog2++;
n >>= 1;
end
end
endfunction
endmodule
On Mon, Feb 8, 2016 at 5:13 PM, Stephen Williams <st...@ic...> wrote:
>
> If you make a small but complete example that we cal compile
> for ourselves, we can take a look at this.
>
> On 02/08/2016 12:50 PM, Dan McLeran wrote:
>> I am using iverilog to learn SystemVerilog. I am following along in a
>> digital system design book and am having trouble building one of the
>> examples. The code uses a function to calculate log2:
>>
>> module #(parameter AL = 8, BL = 8, QL = AL + BL) ...
>>
>> logic[clog2(AL):0] count;
>> ...
>> function clog2(input int n);
>> begin
>> clog2 = 0;
>> n--;
>> while(n > 0)
>> begin
>> clog2++;
>> n >>= 1;
>> end
>> end
>> endfunction
>> endmodule
>>
>> I calling iverilog like this:
>>
>> iverilog -g2012 -Wall -o booth booth.sv
>>
>> It seems to get hung processing the loop or detecting n == 0 or
>> something. Is there an easy way
>> to debug this? I was thinking I'd run iverilog within gdb but maybe
>> there is a faster way to determine what is happening?
>>
>> Regards,
>>
>> Dan McLeran
>>
>> ------------------------------------------------------------------------------
>> Site24x7 APM Insight: Get Deep Visibility into Application Performance
>> APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
>> Monitor end-to-end web transactions and take corrective actions now
>> Troubleshoot faster and improve end-user experience. Signup Now!
>> http://pubads.g.doubleclick.net/gampad/clk?id=272487151&iu=/4140
>> _______________________________________________
>> Iverilog-devel mailing list
>> Ive...@li...
>> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>>
>
>
> --
> Steve Williams "The woods are lovely, dark and deep.
> steve at icarus.com But I have promises to keep,
> http://www.icarus.com and lines to code before I sleep,
> http://www.picturel.com And lines to code before I sleep."
>
> ------------------------------------------------------------------------------
> Site24x7 APM Insight: Get Deep Visibility into Application Performance
> APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
> Monitor end-to-end web transactions and take corrective actions now
> Troubleshoot faster and improve end-user experience. Signup Now!
> http://pubads.g.doubleclick.net/gampad/clk?id=272487151&iu=/4140
> _______________________________________________
> Iverilog-devel mailing list
> Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
|
|
From: Cary R. <cy...@ya...> - 2016-02-09 07:23:53
|
I can confirm that this does fail using both V10 and development.I'm guessing it has something to do with the constant function code and the SystemVerilog type or operators. I do not have time to look at this right now. This looks like valid code and is likely a problem in Icarus so not something that is easy for an end user to debug. If you feel adventurous then look at the constant function code in the compiler (eval_tree.cc, etc.) and add appropriate debug output to see what is going on.
Cary
On Monday, February 8, 2016 8:02 PM, Dan McLeran <dan...@gm...> wrote:
Thanks. Here is a simple example. Using the function clog2 in the
declaration of the logic array causes the failure. Using clog2 in the
sequential logic appears to work.
iverilog -g2012 -Wall -o example example.sv
//example.sv
module example #(parameter N = 8) (output logic[3:0] result, input logic clk);
//logic[clog2(N):0] temp; //comment this line back in to see the failure
always@(posedge clk)
result <= clog2(N);
function int clog2(input int n);
begin
clog2 = 0;
n--;
while(n > 0)
begin
clog2++;
n >>= 1;
end
end
endfunction
endmodule
On Mon, Feb 8, 2016 at 5:13 PM, Stephen Williams <st...@ic...> wrote:
>
> If you make a small but complete example that we cal compile
> for ourselves, we can take a look at this.
>
> On 02/08/2016 12:50 PM, Dan McLeran wrote:
>> I am using iverilog to learn SystemVerilog. I am following along in a
>> digital system design book and am having trouble building one of the
>> examples. The code uses a function to calculate log2:
>>
>> module #(parameter AL = 8, BL = 8, QL = AL + BL) ...
>>
>> logic[clog2(AL):0] count;
>> ...
>> function clog2(input int n);
>> begin
>> clog2 = 0;
>> n--;
>> while(n > 0)
>> begin
>> clog2++;
>> n >>= 1;
>> end
>> end
>> endfunction
>> endmodule
>>
>> I calling iverilog like this:
>>
>> iverilog -g2012 -Wall -o booth booth.sv
>>
>> It seems to get hung processing the loop or detecting n == 0 or
>> something. Is there an easy way
>> to debug this? I was thinking I'd run iverilog within gdb but maybe
>> there is a faster way to determine what is happening?
>>
>> Regards,
>>
>> Dan McLeran
>>
>> ------------------------------------------------------------------------------
>> Site24x7 APM Insight: Get Deep Visibility into Application Performance
>> APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
>> Monitor end-to-end web transactions and take corrective actions now
>> Troubleshoot faster and improve end-user experience. Signup Now!
>> http://pubads.g.doubleclick.net/gampad/clk?id=272487151&iu=/4140
>> _______________________________________________
>> Iverilog-devel mailing list
>> Ive...@li...
>> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>>
>
>
> --
> Steve Williams "The woods are lovely, dark and deep.
> steve at icarus.com But I have promises to keep,
> http://www.icarus.com and lines to code before I sleep,
> http://www.picturel.com And lines to code before I sleep."
>
> ------------------------------------------------------------------------------
> Site24x7 APM Insight: Get Deep Visibility into Application Performance
> APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
> Monitor end-to-end web transactions and take corrective actions now
> Troubleshoot faster and improve end-user experience. Signup Now!
> http://pubads.g.doubleclick.net/gampad/clk?id=272487151&iu=/4140
> _______________________________________________
> Iverilog-devel mailing list
> Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
------------------------------------------------------------------------------
Site24x7 APM Insight: Get Deep Visibility into Application Performance
APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
Monitor end-to-end web transactions and take corrective actions now
Troubleshoot faster and improve end-user experience. Signup Now!
http://pubads.g.doubleclick.net/gampad/clk?id=272487151&iu=/4140
_______________________________________________
Iverilog-devel mailing list
Ive...@li...
https://lists.sourceforge.net/lists/listinfo/iverilog-devel
|
|
From: Cary R. <cy...@ya...> - 2016-02-09 07:28:15
|
And as a further note the Verilog equivalent of this code does work correctly.
On Monday, February 8, 2016 11:20 PM, Cary R. <cy...@ya...> wrote:
I can confirm that this does fail using both V10 and development.I'm guessing it has something to do with the constant function code and the SystemVerilog type or operators. I do not have time to look at this right now. This looks like valid code and is likely a problem in Icarus so not something that is easy for an end user to debug. If you feel adventurous then look at the constant function code in the compiler (eval_tree.cc, etc.) and add appropriate debug output to see what is going on.
Cary
On Monday, February 8, 2016 8:02 PM, Dan McLeran <dan...@gm...> wrote:
Thanks. Here is a simple example. Using the function clog2 in the
declaration of the logic array causes the failure. Using clog2 in the
sequential logic appears to work.
iverilog -g2012 -Wall -o example example.sv
//example.sv
module example #(parameter N = 8) (output logic[3:0] result, input logic clk);
//logic[clog2(N):0] temp; //comment this line back in to see the failure
always@(posedge clk)
result <= clog2(N);
function int clog2(input int n);
begin
clog2 = 0;
n--;
while(n > 0)
begin
clog2++;
n >>= 1;
end
end
endfunction
endmodule
On Mon, Feb 8, 2016 at 5:13 PM, Stephen Williams <st...@ic...> wrote:
>
> If you make a small but complete example that we cal compile
> for ourselves, we can take a look at this.
>
> On 02/08/2016 12:50 PM, Dan McLeran wrote:
>> I am using iverilog to learn SystemVerilog. I am following along in a
>> digital system design book and am having trouble building one of the
>> examples. The code uses a function to calculate log2:
>>
>> module #(parameter AL = 8, BL = 8, QL = AL + BL) ...
>>
>> logic[clog2(AL):0] count;
>> ...
>> function clog2(input int n);
>> begin
>> clog2 = 0;
>> n--;
>> while(n > 0)
>> begin
>> clog2++;
>> n >>= 1;
>> end
>> end
>> endfunction
>> endmodule
>>
>> I calling iverilog like this:
>>
>> iverilog -g2012 -Wall -o booth booth.sv
>>
>> It seems to get hung processing the loop or detecting n == 0 or
>> something. Is there an easy way
>> to debug this? I was thinking I'd run iverilog within gdb but maybe
>> there is a faster way to determine what is happening?
>>
>> Regards,
>>
>> Dan McLeran
>>
>> ------------------------------------------------------------------------------
>> Site24x7 APM Insight: Get Deep Visibility into Application Performance
>> APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
>> Monitor end-to-end web transactions and take corrective actions now
>> Troubleshoot faster and improve end-user experience. Signup Now!
>> http://pubads.g.doubleclick.net/gampad/clk?id=272487151&iu=/4140
>> _______________________________________________
>> Iverilog-devel mailing list
>> Ive...@li...
>> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>>
>
>
> --
> Steve Williams "The woods are lovely, dark and deep.
> steve at icarus.com But I have promises to keep,
> http://www.icarus.com and lines to code before I sleep,
> http://www.picturel.com And lines to code before I sleep."
>
> ------------------------------------------------------------------------------
> Site24x7 APM Insight: Get Deep Visibility into Application Performance
> APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
> Monitor end-to-end web transactions and take corrective actions now
> Troubleshoot faster and improve end-user experience. Signup Now!
> http://pubads.g.doubleclick.net/gampad/clk?id=272487151&iu=/4140
> _______________________________________________
> Iverilog-devel mailing list
> Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
------------------------------------------------------------------------------
Site24x7 APM Insight: Get Deep Visibility into Application Performance
APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
Monitor end-to-end web transactions and take corrective actions now
Troubleshoot faster and improve end-user experience. Signup Now!
http://pubads.g.doubleclick.net/gampad/clk?id=272487151&iu=/4140
_______________________________________________
Iverilog-devel mailing list
Ive...@li...
https://lists.sourceforge.net/lists/listinfo/iverilog-devel
|
|
From: Martin W. <mai...@ma...> - 2016-02-09 09:07:31
|
Cary R. wrote: > I can confirm that this does fail using both V10 and development.I'm > guessing it has something to do with the constant function code and the > SystemVerilog type or operators. I do not have time to look at this right > now. This looks like valid code and is likely a problem in Icarus so not > something that is easy for an end user to debug. If you feel adventurous > then look at the constant function code in the compiler (eval_tree.cc, > etc.) and add appropriate debug output to see what is going on. Cary Yes, running with the -deval_tree debugging option shows that all the SV merged operator/assignments (++, --, >>=) don't work in a constant context. Martin |
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From: Martin W. <mai...@ma...> - 2016-02-23 08:36:52
|
Martin Whitaker wrote: > Cary R. wrote: >> I can confirm that this does fail using both V10 and development.I'm >> guessing it has something to do with the constant function code and the >> SystemVerilog type or operators. I do not have time to look at this right >> now. This looks like valid code and is likely a problem in Icarus so not >> something that is easy for an end user to debug. If you feel adventurous >> then look at the constant function code in the compiler (eval_tree.cc, >> etc.) and add appropriate debug output to see what is going on. Cary > > Yes, running with the -deval_tree debugging option shows that all the SV > merged operator/assignments (++, --, >>=) don't work in a constant context. > I've pushed a fix for this to both the devel and v10 branches. I've tested basic operation, but not explored mixing types, sizes, part selects, etc. Not currently supported are: - assignment to concatenations - increment/decrement operators inside expressions Operation on real operands is implemented but not tested, because tgt-vvp doesn't currently support this either. Martin |
|
From: Martin W. <mai...@ma...> - 2016-02-23 23:13:06
|
Martin Whitaker wrote: > Martin Whitaker wrote: >> Yes, running with the -deval_tree debugging option shows that all the SV >> merged operator/assignments (++, --, >>=) don't work in a constant context. >> > I've pushed a fix for this to both the devel and v10 branches. I've tested > basic operation, but not explored mixing types, sizes, part selects, etc. Not > currently supported are: > > - assignment to concatenations > - increment/decrement operators inside expressions > > Operation on real operands is implemented but not tested, because tgt-vvp > doesn't currently support this either. I've now added the missing functionality to tgt-vvp and fixed a few other bugs in this area. |
|
From: Dan M. <dan...@gm...> - 2016-02-25 13:35:48
|
Awesome, thanks! I haven't had time for fun stuff lately but will check it out when I get a chance. On Tue, Feb 23, 2016 at 4:12 PM, Martin Whitaker <mai...@ma...> wrote: > Martin Whitaker wrote: >> Martin Whitaker wrote: >>> Yes, running with the -deval_tree debugging option shows that all the SV >>> merged operator/assignments (++, --, >>=) don't work in a constant context. >>> >> I've pushed a fix for this to both the devel and v10 branches. I've tested >> basic operation, but not explored mixing types, sizes, part selects, etc. Not >> currently supported are: >> >> - assignment to concatenations >> - increment/decrement operators inside expressions >> >> Operation on real operands is implemented but not tested, because tgt-vvp >> doesn't currently support this either. > > I've now added the missing functionality to tgt-vvp and fixed a few other bugs > in this area. > > > ------------------------------------------------------------------------------ > Site24x7 APM Insight: Get Deep Visibility into Application Performance > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month > Monitor end-to-end web transactions and take corrective actions now > Troubleshoot faster and improve end-user experience. Signup Now! > http://pubads.g.doubleclick.net/gampad/clk?id=272487151&iu=/4140 > _______________________________________________ > Iverilog-devel mailing list > Ive...@li... > https://lists.sourceforge.net/lists/listinfo/iverilog-devel |
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