iverilog-devel

[Iverilog-devel] system verilog syntax error.

[Lonnie G. <lg...@sr...>]

I tried the latest snapshot:
Icarus Verilog version 0.10.0 (devel) (s20130827)

I get the following errors from this code in an altera system verilog
file. 

Lonnie

/opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1360: syntax error
/opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1360: error:
malformed statement
/opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1361: syntax error
/opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1361: error:
malformed statement
/opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1362: syntax error
/opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1362: error:
malformed statement
/opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1363: syntax error
/opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1363: error:
malformed statement
/opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1364: syntax error
/opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1364: error:
malformed statement

altera .sv file

//--------------------------------------------------------------------------
// Function Name    : strtobits
// Description      : takes in a string where
// each character represents a hexadecimal number, transforms that number into
// 4-bits, concatenates the result and returns it.
//--------------------------------------------------------------------------

function [4*MEM_INIT_STRING_LENGTH -1 : 0]  strtobits;
	input [8*MEM_INIT_STRING_LENGTH : 1] my_string;
	begin

        integer char_idx;  line 1361
	integer bit_idx;        1362
	reg[7:0] my_char;       1363
	reg[3:0] hex_value;     1364
	reg[4*MEM_INIT_STRING_LENGTH - 1 : 0] temp_bits;

Re: [Iverilog-devel] system verilog syntax error.

[Stephen W. <st...@ic...>]

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1


That snapshto is fairly old. I should make a new snapshot.
SystemVerilog support is in active development, the latest
stuff is in the git master branch.

On 08/01/2014 09:15 AM, Lonnie Gliem wrote:
> I tried the latest snapshot: Icarus Verilog version 0.10.0 (devel)
> (s20130827)
> 
> I get the following errors from this code in an altera system
> verilog file.
> 
> Lonnie
> 
> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1360: syntax
> error /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1360:
> error: malformed statement 
> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1361: syntax
> error /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1361:
> error: malformed statement 
> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1362: syntax
> error /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1362:
> error: malformed statement 
> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1363: syntax
> error /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1363:
> error: malformed statement 
> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1364: syntax
> error /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1364:
> error: malformed statement
> 
> altera .sv file
> 
> //--------------------------------------------------------------------------
>
> 
// Function Name    : strtobits
> // Description      : takes in a string where // each character
> represents a hexadecimal number, transforms that number into //
> 4-bits, concatenates the result and returns it. 
> //--------------------------------------------------------------------------
>
>  function [4*MEM_INIT_STRING_LENGTH -1 : 0]  strtobits; input
> [8*MEM_INIT_STRING_LENGTH : 1] my_string; begin
> 
> integer char_idx;  line 1361 integer bit_idx;        1362 reg[7:0]
> my_char;       1363 reg[3:0] hex_value;     1364 
> reg[4*MEM_INIT_STRING_LENGTH - 1 : 0] temp_bits;
> 
> 
> ------------------------------------------------------------------------------
>
> 
Want fast and easy access to all the code in your enterprise? Index and
> search up to 200,000 lines of code with a free copy of Black Duck 
> Code Sight - the same software that powers the world's largest
> code search on Ohloh, the Black Duck Open Hub! Try it now. 
> http://p.sf.net/sfu/bds 
> _______________________________________________ Iverilog-devel
> mailing list Ive...@li... 
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> 


- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/

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Re: [Iverilog-devel] system verilog syntax error.

[Lonnie L G. <lg...@sr...>]

Where do I find the git master branch?

-----Original Message-----
From: Stephen Williams [mailto:st...@ic...] 
Sent: Friday, August 01, 2014 11:20 AM
To: ive...@li...
Subject: Re: [Iverilog-devel] system verilog syntax error.

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1


That snapshto is fairly old. I should make a new snapshot.
SystemVerilog support is in active development, the latest stuff is in the
git master branch.

On 08/01/2014 09:15 AM, Lonnie Gliem wrote:
> I tried the latest snapshot: Icarus Verilog version 0.10.0 (devel)
> (s20130827)
> 
> I get the following errors from this code in an altera system verilog 
> file.
> 
> Lonnie
> 
> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1360: syntax error 
> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1360:
> error: malformed statement
> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1361: syntax error 
> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1361:
> error: malformed statement
> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1362: syntax error 
> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1362:
> error: malformed statement
> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1363: syntax error 
> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1363:
> error: malformed statement
> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1364: syntax error 
> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1364:
> error: malformed statement
> 
> altera .sv file
> 
> //--------------------------------------------------------------------
> ------
>
> 
// Function Name    : strtobits
> // Description      : takes in a string where // each character
> represents a hexadecimal number, transforms that number into // 
> 4-bits, concatenates the result and returns it.
> //--------------------------------------------------------------------
> ------
>
>  function [4*MEM_INIT_STRING_LENGTH -1 : 0]  strtobits; input 
> [8*MEM_INIT_STRING_LENGTH : 1] my_string; begin
> 
> integer char_idx;  line 1361 integer bit_idx;        1362 reg[7:0]
> my_char;       1363 reg[3:0] hex_value;     1364 
> reg[4*MEM_INIT_STRING_LENGTH - 1 : 0] temp_bits;
> 
> 
> ----------------------------------------------------------------------
> --------
>
> 
Want fast and easy access to all the code in your enterprise? Index and
> search up to 200,000 lines of code with a free copy of Black Duck Code 
> Sight - the same software that powers the world's largest code search 
> on Ohloh, the Black Duck Open Hub! Try it now.
> http://p.sf.net/sfu/bds
> _______________________________________________ Iverilog-devel mailing 
> list Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> 


- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.19 (GNU/Linux)
Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/

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=ElWd
-----END PGP SIGNATURE-----

----------------------------------------------------------------------------
--
Want fast and easy access to all the code in your enterprise? Index and
search up to 200,000 lines of code with a free copy of Black Duck
Code Sight - the same software that powers the world's largest code
search on Ohloh, the Black Duck Open Hub! Try it now.
http://p.sf.net/sfu/bds
_______________________________________________
Iverilog-devel mailing list
Ive...@li...
https://lists.sourceforge.net/lists/listinfo/iverilog-devel

Re: [Iverilog-devel] system verilog syntax error.

[Stephen W. <st...@ic...>]

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1


You would need to extract it using "git". There is a detailed
installation guide here, which includes a chapter on getting
the source from git:

  <http://iverilog.wikia.com/wiki/Installation_Guide>

Your request has pointed out an issue, that we really need to
make a new snapshot. I'll see about doing that today.


On 08/01/2014 09:22 AM, Lonnie L Gliem wrote:
> Where do I find the git master branch?
> 
> -----Original Message----- From: Stephen Williams
> [mailto:st...@ic...] Sent: Friday, August 01, 2014 11:20 AM 
> To: ive...@li... Subject: Re:
> [Iverilog-devel] system verilog syntax error.
> 
> 
> That snapshto is fairly old. I should make a new snapshot. 
> SystemVerilog support is in active development, the latest stuff is
> in the git master branch.
> 
> On 08/01/2014 09:15 AM, Lonnie Gliem wrote:
>> I tried the latest snapshot: Icarus Verilog version 0.10.0
>> (devel) (s20130827)
> 
>> I get the following errors from this code in an altera system
>> verilog file.
> 
>> Lonnie
> 
>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1360: syntax
>> error /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1360: 
>> error: malformed statement 
>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1361: syntax
>> error /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1361: 
>> error: malformed statement 
>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1362: syntax
>> error /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1362: 
>> error: malformed statement 
>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1363: syntax
>> error /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1363: 
>> error: malformed statement 
>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1364: syntax
>> error /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1364: 
>> error: malformed statement
> 
>> altera .sv file
> 
>> //--------------------------------------------------------------------
>>
>> 
- ------
> 
> 
> // Function Name    : strtobits
>> // Description      : takes in a string where // each character 
>> represents a hexadecimal number, transforms that number into // 
>> 4-bits, concatenates the result and returns it. 
>> //--------------------------------------------------------------------
>>
>> 
- ------
> 
>> function [4*MEM_INIT_STRING_LENGTH -1 : 0]  strtobits; input 
>> [8*MEM_INIT_STRING_LENGTH : 1] my_string; begin
> 
>> integer char_idx;  line 1361 integer bit_idx;        1362
>> reg[7:0] my_char;       1363 reg[3:0] hex_value;     1364 
>> reg[4*MEM_INIT_STRING_LENGTH - 1 : 0] temp_bits;
> 
> 
>> ----------------------------------------------------------------------
>>
>> 
- --------
> 
> 
> Want fast and easy access to all the code in your enterprise? Index
> and
>> search up to 200,000 lines of code with a free copy of Black Duck
>> Code Sight - the same software that powers the world's largest
>> code search on Ohloh, the Black Duck Open Hub! Try it now. 
>> http://p.sf.net/sfu/bds 
>> _______________________________________________ Iverilog-devel
>> mailing list Ive...@li... 
>> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> 
> 
> 
> 
> ----------------------------------------------------------------------------
>
> 
- --
> Want fast and easy access to all the code in your enterprise? Index
> and search up to 200,000 lines of code with a free copy of Black
> Duck Code Sight - the same software that powers the world's largest
> code search on Ohloh, the Black Duck Open Hub! Try it now. 
> http://p.sf.net/sfu/bds 
> _______________________________________________ Iverilog-devel
> mailing list Ive...@li... 
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> 
> 
> 
> ------------------------------------------------------------------------------
>
> 
Want fast and easy access to all the code in your enterprise? Index and
> search up to 200,000 lines of code with a free copy of Black Duck 
> Code Sight - the same software that powers the world's largest
> code search on Ohloh, the Black Duck Open Hub! Try it now. 
> http://p.sf.net/sfu/bds 
> _______________________________________________ Iverilog-devel
> mailing list Ive...@li... 
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> 

- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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Version: GnuPG v2.0.19 (GNU/Linux)
Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/

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Re: [Iverilog-devel] system verilog syntax error.

[Lonnie L G. <lg...@sr...>]

I think I will just wait for the snapshot let me know when it is ready. 

Thanks
Lonnie


-----Original Message-----
From: Stephen Williams [mailto:st...@ic...] 
Sent: Friday, August 01, 2014 11:27 AM
To: ive...@li...
Subject: Re: [Iverilog-devel] system verilog syntax error.

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1


You would need to extract it using "git". There is a detailed installation
guide here, which includes a chapter on getting the source from git:

  <http://iverilog.wikia.com/wiki/Installation_Guide>

Your request has pointed out an issue, that we really need to make a new
snapshot. I'll see about doing that today.


On 08/01/2014 09:22 AM, Lonnie L Gliem wrote:
> Where do I find the git master branch?
> 
> -----Original Message----- From: Stephen Williams 
> [mailto:st...@ic...] Sent: Friday, August 01, 2014 11:20 AM
> To: ive...@li... Subject: Re:
> [Iverilog-devel] system verilog syntax error.
> 
> 
> That snapshto is fairly old. I should make a new snapshot. 
> SystemVerilog support is in active development, the latest stuff is in 
> the git master branch.
> 
> On 08/01/2014 09:15 AM, Lonnie Gliem wrote:
>> I tried the latest snapshot: Icarus Verilog version 0.10.0
>> (devel) (s20130827)
> 
>> I get the following errors from this code in an altera system verilog 
>> file.
> 
>> Lonnie
> 
>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1360: syntax 
>> error /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1360:
>> error: malformed statement
>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1361: syntax 
>> error /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1361:
>> error: malformed statement
>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1362: syntax 
>> error /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1362:
>> error: malformed statement
>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1363: syntax 
>> error /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1363:
>> error: malformed statement
>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1364: syntax 
>> error /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1364:
>> error: malformed statement
> 
>> altera .sv file
> 
>> //-------------------------------------------------------------------
>> -
>>
>> 
- ------
> 
> 
> // Function Name    : strtobits
>> // Description      : takes in a string where // each character 
>> represents a hexadecimal number, transforms that number into // 
>> 4-bits, concatenates the result and returns it.
>> //-------------------------------------------------------------------
>> -
>>
>> 
- ------
> 
>> function [4*MEM_INIT_STRING_LENGTH -1 : 0]  strtobits; input 
>> [8*MEM_INIT_STRING_LENGTH : 1] my_string; begin
> 
>> integer char_idx;  line 1361 integer bit_idx;        1362
>> reg[7:0] my_char;       1363 reg[3:0] hex_value;     1364 
>> reg[4*MEM_INIT_STRING_LENGTH - 1 : 0] temp_bits;
> 
> 
>> ---------------------------------------------------------------------
>> -
>>
>> 
- --------
> 
> 
> Want fast and easy access to all the code in your enterprise? Index 
> and
>> search up to 200,000 lines of code with a free copy of Black Duck 
>> Code Sight - the same software that powers the world's largest code 
>> search on Ohloh, the Black Duck Open Hub! Try it now.
>> http://p.sf.net/sfu/bds
>> _______________________________________________ Iverilog-devel 
>> mailing list Ive...@li...
>> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> 
> 
> 
> 
> ----------------------------------------------------------------------
> ------
>
> 
- --
> Want fast and easy access to all the code in your enterprise? Index 
> and search up to 200,000 lines of code with a free copy of Black Duck 
> Code Sight - the same software that powers the world's largest code 
> search on Ohloh, the Black Duck Open Hub! Try it now.
> http://p.sf.net/sfu/bds
> _______________________________________________ Iverilog-devel mailing 
> list Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> 
> 
> 
> ----------------------------------------------------------------------
> --------
>
> 
Want fast and easy access to all the code in your enterprise? Index and
> search up to 200,000 lines of code with a free copy of Black Duck Code 
> Sight - the same software that powers the world's largest code search 
> on Ohloh, the Black Duck Open Hub! Try it now.
> http://p.sf.net/sfu/bds
> _______________________________________________ Iverilog-devel mailing 
> list Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> 

- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.19 (GNU/Linux)
Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/

iEYEARECAAYFAlPbv9cACgkQrPt1Sc2b3imDbQCePDkCMadVLNb0rFpd+f2xilg6
XYIAniAipfueSZNNHOFS9kZBu0Ggxtzm
=jroS
-----END PGP SIGNATURE-----

----------------------------------------------------------------------------
--
Want fast and easy access to all the code in your enterprise? Index and
search up to 200,000 lines of code with a free copy of Black Duck
Code Sight - the same software that powers the world's largest code
search on Ohloh, the Black Duck Open Hub! Try it now.
http://p.sf.net/sfu/bds
_______________________________________________
Iverilog-devel mailing list
Ive...@li...
https://lists.sourceforge.net/lists/listinfo/iverilog-devel

Re: [Iverilog-devel] system verilog syntax error.

[Stephen W. <st...@ic...>]

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1


I just tossed together a snapshot here:

<ftp://ftp.icarus.com/pub/eda/verilog/snapshots/verilog-20140801.tar.gz>

It's been a year since the last snapshot, so why the heck not?

There has also been talk of making a new 0.9 release, and possible
talk of a version 10 release as well, although the 0.9.8 would
come first, since the SystemVerilog work is still being furiously
worked on.

On 08/01/2014 09:55 AM, Lonnie L Gliem wrote:
> I think I will just wait for the snapshot let me know when it is
> ready.
> 
> Thanks Lonnie
> 
> 
> -----Original Message----- From: Stephen Williams
> [mailto:st...@ic...] Sent: Friday, August 01, 2014 11:27 AM 
> To: ive...@li... Subject: Re:
> [Iverilog-devel] system verilog syntax error.
> 
> 
> You would need to extract it using "git". There is a detailed
> installation guide here, which includes a chapter on getting the
> source from git:
> 
> <http://iverilog.wikia.com/wiki/Installation_Guide>
> 
> Your request has pointed out an issue, that we really need to make
> a new snapshot. I'll see about doing that today.
> 
> 
> On 08/01/2014 09:22 AM, Lonnie L Gliem wrote:
>> Where do I find the git master branch?
> 
>> -----Original Message----- From: Stephen Williams 
>> [mailto:st...@ic...] Sent: Friday, August 01, 2014 11:20 AM 
>> To: ive...@li... Subject: Re: 
>> [Iverilog-devel] system verilog syntax error.
> 
> 
>> That snapshto is fairly old. I should make a new snapshot. 
>> SystemVerilog support is in active development, the latest stuff
>> is in the git master branch.
> 
>> On 08/01/2014 09:15 AM, Lonnie Gliem wrote:
>>> I tried the latest snapshot: Icarus Verilog version 0.10.0 
>>> (devel) (s20130827)
> 
>>> I get the following errors from this code in an altera system
>>> verilog file.
> 
>>> Lonnie
> 
>>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1360:
>>> syntax error
>>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1360: 
>>> error: malformed statement 
>>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1361:
>>> syntax error
>>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1361: 
>>> error: malformed statement 
>>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1362:
>>> syntax error
>>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1362: 
>>> error: malformed statement 
>>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1363:
>>> syntax error
>>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1363: 
>>> error: malformed statement 
>>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1364:
>>> syntax error
>>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1364: 
>>> error: malformed statement
> 
>>> altera .sv file
> 
>>> //-------------------------------------------------------------------
>>>
>>> 
- -
>>> 
>>> 
> ------
> 
> 
>> // Function Name    : strtobits
>>> // Description      : takes in a string where // each character
>>>  represents a hexadecimal number, transforms that number into
>>> // 4-bits, concatenates the result and returns it. 
>>> //-------------------------------------------------------------------
>>>
>>> 
- -
>>> 
>>> 
> ------
> 
>>> function [4*MEM_INIT_STRING_LENGTH -1 : 0]  strtobits; input 
>>> [8*MEM_INIT_STRING_LENGTH : 1] my_string; begin
> 
>>> integer char_idx;  line 1361 integer bit_idx;        1362 
>>> reg[7:0] my_char;       1363 reg[3:0] hex_value;     1364 
>>> reg[4*MEM_INIT_STRING_LENGTH - 1 : 0] temp_bits;
> 
> 
>>> ---------------------------------------------------------------------
>>>
>>> 
- -
>>> 
>>> 
> --------
> 
> 
>> Want fast and easy access to all the code in your enterprise?
>> Index and
>>> search up to 200,000 lines of code with a free copy of Black
>>> Duck Code Sight - the same software that powers the world's
>>> largest code search on Ohloh, the Black Duck Open Hub! Try it
>>> now. http://p.sf.net/sfu/bds 
>>> _______________________________________________ Iverilog-devel
>>>  mailing list Ive...@li... 
>>> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> 
> 
> 
> 
>> ----------------------------------------------------------------------
>>
>> 
- ------
> 
> 
> --
>> Want fast and easy access to all the code in your enterprise?
>> Index and search up to 200,000 lines of code with a free copy of
>> Black Duck Code Sight - the same software that powers the world's
>> largest code search on Ohloh, the Black Duck Open Hub! Try it
>> now. http://p.sf.net/sfu/bds 
>> _______________________________________________ Iverilog-devel
>> mailing list Ive...@li... 
>> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> 
> 
> 
>> ----------------------------------------------------------------------
>>
>> 
- --------
> 
> 
> Want fast and easy access to all the code in your enterprise? Index
> and
>> search up to 200,000 lines of code with a free copy of Black Duck
>> Code Sight - the same software that powers the world's largest
>> code search on Ohloh, the Black Duck Open Hub! Try it now. 
>> http://p.sf.net/sfu/bds 
>> _______________________________________________ Iverilog-devel
>> mailing list Ive...@li... 
>> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> 
> 
> 
> ----------------------------------------------------------------------------
>
> 
- --
> Want fast and easy access to all the code in your enterprise? Index
> and search up to 200,000 lines of code with a free copy of Black
> Duck Code Sight - the same software that powers the world's largest
> code search on Ohloh, the Black Duck Open Hub! Try it now. 
> http://p.sf.net/sfu/bds 
> _______________________________________________ Iverilog-devel
> mailing list Ive...@li... 
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> 
> 
> 
> ------------------------------------------------------------------------------
>
> 
Want fast and easy access to all the code in your enterprise? Index and
> search up to 200,000 lines of code with a free copy of Black Duck 
> Code Sight - the same software that powers the world's largest
> code search on Ohloh, the Black Duck Open Hub! Try it now. 
> http://p.sf.net/sfu/bds 
> _______________________________________________ Iverilog-devel
> mailing list Ive...@li... 
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> 

- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.19 (GNU/Linux)
Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/

iEYEARECAAYFAlPcCeAACgkQrPt1Sc2b3inOHQCfQsnefYYkD/8OP4Di8nhhq3Ky
1pQAn2ML+75tBbcZTJc8F2xEWppgt8ro
=wiYa
-----END PGP SIGNATURE-----

Re: [Iverilog-devel] system verilog syntax error.

[Lonnie L G. <lg...@sr...>]

I updated to the latest snapshot and now I get this error which seems
strange?

Using language generation: IEEE1800-2012,no-specify,xtypes,icarus-misc
PARSING INPUT
/opt/altera12.1/quartus/eda/sim_lib/altera_primitives.v:83: syntax error
I give up.


`timescale 1 ps / 1 ps
module soft (in, out);    <-------- This is line 83.
    input in;
    output out;

    assign out = in;
endmodule

-----Original Message-----
From: Stephen Williams [mailto:st...@ic...] 
Sent: Friday, August 01, 2014 4:43 PM
To: ive...@li...
Subject: Re: [Iverilog-devel] system verilog syntax error.

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1


I just tossed together a snapshot here:

<ftp://ftp.icarus.com/pub/eda/verilog/snapshots/verilog-20140801.tar.gz>

It's been a year since the last snapshot, so why the heck not?

There has also been talk of making a new 0.9 release, and possible talk of a
version 10 release as well, although the 0.9.8 would come first, since the
SystemVerilog work is still being furiously worked on.

On 08/01/2014 09:55 AM, Lonnie L Gliem wrote:
> I think I will just wait for the snapshot let me know when it is 
> ready.
> 
> Thanks Lonnie
> 
> 
> -----Original Message----- From: Stephen Williams 
> [mailto:st...@ic...] Sent: Friday, August 01, 2014 11:27 AM
> To: ive...@li... Subject: Re:
> [Iverilog-devel] system verilog syntax error.
> 
> 
> You would need to extract it using "git". There is a detailed 
> installation guide here, which includes a chapter on getting the 
> source from git:
> 
> <http://iverilog.wikia.com/wiki/Installation_Guide>
> 
> Your request has pointed out an issue, that we really need to make a 
> new snapshot. I'll see about doing that today.
> 
> 
> On 08/01/2014 09:22 AM, Lonnie L Gliem wrote:
>> Where do I find the git master branch?
> 
>> -----Original Message----- From: Stephen Williams 
>> [mailto:st...@ic...] Sent: Friday, August 01, 2014 11:20 AM
>> To: ive...@li... Subject: Re: 
>> [Iverilog-devel] system verilog syntax error.
> 
> 
>> That snapshto is fairly old. I should make a new snapshot. 
>> SystemVerilog support is in active development, the latest stuff is 
>> in the git master branch.
> 
>> On 08/01/2014 09:15 AM, Lonnie Gliem wrote:
>>> I tried the latest snapshot: Icarus Verilog version 0.10.0
>>> (devel) (s20130827)
> 
>>> I get the following errors from this code in an altera system 
>>> verilog file.
> 
>>> Lonnie
> 
>>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1360:
>>> syntax error
>>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1360: 
>>> error: malformed statement
>>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1361:
>>> syntax error
>>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1361: 
>>> error: malformed statement
>>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1362:
>>> syntax error
>>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1362: 
>>> error: malformed statement
>>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1363:
>>> syntax error
>>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1363: 
>>> error: malformed statement
>>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1364:
>>> syntax error
>>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1364: 
>>> error: malformed statement
> 
>>> altera .sv file
> 
>>> //------------------------------------------------------------------
>>> -
>>>
>>> 
- -
>>> 
>>> 
> ------
> 
> 
>> // Function Name    : strtobits
>>> // Description      : takes in a string where // each character
>>>  represents a hexadecimal number, transforms that number into // 
>>> 4-bits, concatenates the result and returns it.
>>> //------------------------------------------------------------------
>>> -
>>>
>>> 
- -
>>> 
>>> 
> ------
> 
>>> function [4*MEM_INIT_STRING_LENGTH -1 : 0]  strtobits; input 
>>> [8*MEM_INIT_STRING_LENGTH : 1] my_string; begin
> 
>>> integer char_idx;  line 1361 integer bit_idx;        1362 
>>> reg[7:0] my_char;       1363 reg[3:0] hex_value;     1364 
>>> reg[4*MEM_INIT_STRING_LENGTH - 1 : 0] temp_bits;
> 
> 
>>> --------------------------------------------------------------------
>>> -
>>>
>>> 
- -
>>> 
>>> 
> --------
> 
> 
>> Want fast and easy access to all the code in your enterprise?
>> Index and
>>> search up to 200,000 lines of code with a free copy of Black Duck 
>>> Code Sight - the same software that powers the world's largest code 
>>> search on Ohloh, the Black Duck Open Hub! Try it now. 
>>> http://p.sf.net/sfu/bds 
>>> _______________________________________________ Iverilog-devel  
>>> mailing list Ive...@li...
>>> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> 
> 
> 
> 
>> ---------------------------------------------------------------------
>> -
>>
>> 
- ------
> 
> 
> --
>> Want fast and easy access to all the code in your enterprise?
>> Index and search up to 200,000 lines of code with a free copy of 
>> Black Duck Code Sight - the same software that powers the world's 
>> largest code search on Ohloh, the Black Duck Open Hub! Try it now. 
>> http://p.sf.net/sfu/bds 
>> _______________________________________________ Iverilog-devel 
>> mailing list Ive...@li...
>> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> 
> 
> 
>> ---------------------------------------------------------------------
>> -
>>
>> 
- --------
> 
> 
> Want fast and easy access to all the code in your enterprise? Index 
> and
>> search up to 200,000 lines of code with a free copy of Black Duck 
>> Code Sight - the same software that powers the world's largest code 
>> search on Ohloh, the Black Duck Open Hub! Try it now.
>> http://p.sf.net/sfu/bds
>> _______________________________________________ Iverilog-devel 
>> mailing list Ive...@li...
>> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> 
> 
> 
> ----------------------------------------------------------------------
> ------
>
> 
- --
> Want fast and easy access to all the code in your enterprise? Index 
> and search up to 200,000 lines of code with a free copy of Black Duck 
> Code Sight - the same software that powers the world's largest code 
> search on Ohloh, the Black Duck Open Hub! Try it now.
> http://p.sf.net/sfu/bds
> _______________________________________________ Iverilog-devel mailing 
> list Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> 
> 
> 
> ----------------------------------------------------------------------
> --------
>
> 
Want fast and easy access to all the code in your enterprise? Index and
> search up to 200,000 lines of code with a free copy of Black Duck Code 
> Sight - the same software that powers the world's largest code search 
> on Ohloh, the Black Duck Open Hub! Try it now.
> http://p.sf.net/sfu/bds
> _______________________________________________ Iverilog-devel mailing 
> list Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> 

- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.19 (GNU/Linux)
Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/

iEYEARECAAYFAlPcCeAACgkQrPt1Sc2b3inOHQCfQsnefYYkD/8OP4Di8nhhq3Ky
1pQAn2ML+75tBbcZTJc8F2xEWppgt8ro
=wiYa
-----END PGP SIGNATURE-----

----------------------------------------------------------------------------
--
Want fast and easy access to all the code in your enterprise? Index and
search up to 200,000 lines of code with a free copy of Black Duck
Code Sight - the same software that powers the world's largest code
search on Ohloh, the Black Duck Open Hub! Try it now.
http://p.sf.net/sfu/bds
_______________________________________________
Iverilog-devel mailing list
Ive...@li...
https://lists.sourceforge.net/lists/listinfo/iverilog-devel

Re: [Iverilog-devel] system verilog syntax error.

[Iztok J. <izt...@gm...>]

The source is not correct, this is what I get from ncsim:

$ irun soft.sv
irun: 14.10-p001: (c) Copyright 1995-2014 Cadence Design Systems, Inc.
file: soft.sv
module soft (in, out);
          |
ncvlog: *E,EXPMDN (soft.sv,2|10): expecting a module name.
    module worklib.???:sv
        errors: 1, warnings: 0
ncvlog: *F,NOTOPL: no top-level unit found, must have recursive instances.
irun: *E,VLGERR: An error occurred during parsing.  Review the log file for
errors with the code *E and fix those identified problems to proceed.
Exiting with code (status 2).

The module name is a SystemVerilog reserved keyword, see standard:
1800-2012.pdf 18.5 Constraint blocks
I suggest you use syntax highlighting, to avoid reserved keywords.

Regards,
Iztok Jeras


On 5 August 2014 15:18, Lonnie L Gliem <lg...@sr...> wrote:

> I updated to the latest snapshot and now I get this error which seems
> strange?
>
> Using language generation: IEEE1800-2012,no-specify,xtypes,icarus-misc
> PARSING INPUT
> /opt/altera12.1/quartus/eda/sim_lib/altera_primitives.v:83: syntax error
> I give up.
>
>
> `timescale 1 ps / 1 ps
> module soft (in, out);    <-------- This is line 83.
>     input in;
>     output out;
>
>     assign out = in;
> endmodule
>
> -----Original Message-----
> From: Stephen Williams [mailto:st...@ic...]
> Sent: Friday, August 01, 2014 4:43 PM
> To: ive...@li...
> Subject: Re: [Iverilog-devel] system verilog syntax error.
>
> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA1
>
>
> I just tossed together a snapshot here:
>
> <ftp://ftp.icarus.com/pub/eda/verilog/snapshots/verilog-20140801.tar.gz>
>
> It's been a year since the last snapshot, so why the heck not?
>
> There has also been talk of making a new 0.9 release, and possible talk of
> a
> version 10 release as well, although the 0.9.8 would come first, since the
> SystemVerilog work is still being furiously worked on.
>
> On 08/01/2014 09:55 AM, Lonnie L Gliem wrote:
> > I think I will just wait for the snapshot let me know when it is
> > ready.
> >
> > Thanks Lonnie
> >
> >
> > -----Original Message----- From: Stephen Williams
> > [mailto:st...@ic...] Sent: Friday, August 01, 2014 11:27 AM
> > To: ive...@li... Subject: Re:
> > [Iverilog-devel] system verilog syntax error.
> >
> >
> > You would need to extract it using "git". There is a detailed
> > installation guide here, which includes a chapter on getting the
> > source from git:
> >
> > <http://iverilog.wikia.com/wiki/Installation_Guide>
> >
> > Your request has pointed out an issue, that we really need to make a
> > new snapshot. I'll see about doing that today.
> >
> >
> > On 08/01/2014 09:22 AM, Lonnie L Gliem wrote:
> >> Where do I find the git master branch?
> >
> >> -----Original Message----- From: Stephen Williams
> >> [mailto:st...@ic...] Sent: Friday, August 01, 2014 11:20 AM
> >> To: ive...@li... Subject: Re:
> >> [Iverilog-devel] system verilog syntax error.
> >
> >
> >> That snapshto is fairly old. I should make a new snapshot.
> >> SystemVerilog support is in active development, the latest stuff is
> >> in the git master branch.
> >
> >> On 08/01/2014 09:15 AM, Lonnie Gliem wrote:
> >>> I tried the latest snapshot: Icarus Verilog version 0.10.0
> >>> (devel) (s20130827)
> >
> >>> I get the following errors from this code in an altera system
> >>> verilog file.
> >
> >>> Lonnie
> >
> >>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1360:
> >>> syntax error
> >>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1360:
> >>> error: malformed statement
> >>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1361:
> >>> syntax error
> >>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1361:
> >>> error: malformed statement
> >>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1362:
> >>> syntax error
> >>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1362:
> >>> error: malformed statement
> >>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1363:
> >>> syntax error
> >>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1363:
> >>> error: malformed statement
> >>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1364:
> >>> syntax error
> >>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1364:
> >>> error: malformed statement
> >
> >>> altera .sv file
> >
> >>> //------------------------------------------------------------------
> >>> -
> >>>
> >>>
> - -
> >>>
> >>>
> > ------
> >
> >
> >> // Function Name    : strtobits
> >>> // Description      : takes in a string where // each character
> >>>  represents a hexadecimal number, transforms that number into //
> >>> 4-bits, concatenates the result and returns it.
> >>> //------------------------------------------------------------------
> >>> -
> >>>
> >>>
> - -
> >>>
> >>>
> > ------
> >
> >>> function [4*MEM_INIT_STRING_LENGTH -1 : 0]  strtobits; input
> >>> [8*MEM_INIT_STRING_LENGTH : 1] my_string; begin
> >
> >>> integer char_idx;  line 1361 integer bit_idx;        1362
> >>> reg[7:0] my_char;       1363 reg[3:0] hex_value;     1364
> >>> reg[4*MEM_INIT_STRING_LENGTH - 1 : 0] temp_bits;
> >
> >
> >>> --------------------------------------------------------------------
> >>> -
> >>>
> >>>
> - -
> >>>
> >>>
> > --------
> >
> >
> >> Want fast and easy access to all the code in your enterprise?
> >> Index and
> >>> search up to 200,000 lines of code with a free copy of Black Duck
> >>> Code Sight - the same software that powers the world's largest code
> >>> search on Ohloh, the Black Duck Open Hub! Try it now.
> >>> http://p.sf.net/sfu/bds
> >>> _______________________________________________ Iverilog-devel
> >>> mailing list Ive...@li...
> >>> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> >
> >
> >
> >
> >> ---------------------------------------------------------------------
> >> -
> >>
> >>
> - ------
> >
> >
> > --
> >> Want fast and easy access to all the code in your enterprise?
> >> Index and search up to 200,000 lines of code with a free copy of
> >> Black Duck Code Sight - the same software that powers the world's
> >> largest code search on Ohloh, the Black Duck Open Hub! Try it now.
> >> http://p.sf.net/sfu/bds
> >> _______________________________________________ Iverilog-devel
> >> mailing list Ive...@li...
> >> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> >
> >
> >
> >> ---------------------------------------------------------------------
> >> -
> >>
> >>
> - --------
> >
> >
> > Want fast and easy access to all the code in your enterprise? Index
> > and
> >> search up to 200,000 lines of code with a free copy of Black Duck
> >> Code Sight - the same software that powers the world's largest code
> >> search on Ohloh, the Black Duck Open Hub! Try it now.
> >> http://p.sf.net/sfu/bds
> >> _______________________________________________ Iverilog-devel
> >> mailing list Ive...@li...
> >> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> >
> >
> >
> > ----------------------------------------------------------------------
> > ------
> >
> >
> - --
> > Want fast and easy access to all the code in your enterprise? Index
> > and search up to 200,000 lines of code with a free copy of Black Duck
> > Code Sight - the same software that powers the world's largest code
> > search on Ohloh, the Black Duck Open Hub! Try it now.
> > http://p.sf.net/sfu/bds
> > _______________________________________________ Iverilog-devel mailing
> > list Ive...@li...
> > https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> >
> >
> >
> > ----------------------------------------------------------------------
> > --------
> >
> >
> Want fast and easy access to all the code in your enterprise? Index and
> > search up to 200,000 lines of code with a free copy of Black Duck Code
> > Sight - the same software that powers the world's largest code search
> > on Ohloh, the Black Duck Open Hub! Try it now.
> > http://p.sf.net/sfu/bds
> > _______________________________________________ Iverilog-devel mailing
> > list Ive...@li...
> > https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> >
>
> - --
> Steve Williams                "The woods are lovely, dark and deep.
> steve at icarus.com           But I have promises to keep,
> http://www.icarus.com         and lines to code before I sleep,
> http://www.picturel.com       And lines to code before I sleep."
> -----BEGIN PGP SIGNATURE-----
> Version: GnuPG v2.0.19 (GNU/Linux)
> Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/
>
> iEYEARECAAYFAlPcCeAACgkQrPt1Sc2b3inOHQCfQsnefYYkD/8OP4Di8nhhq3Ky
> 1pQAn2ML+75tBbcZTJc8F2xEWppgt8ro
> =wiYa
> -----END PGP SIGNATURE-----
>
>
> ----------------------------------------------------------------------------
> --
> Want fast and easy access to all the code in your enterprise? Index and
> search up to 200,000 lines of code with a free copy of Black Duck
> Code Sight - the same software that powers the world's largest code
> search on Ohloh, the Black Duck Open Hub! Try it now.
> http://p.sf.net/sfu/bds
> _______________________________________________
> Iverilog-devel mailing list
> Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>
>
>
>
> ------------------------------------------------------------------------------
> Infragistics Professional
> Build stunning WinForms apps today!
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> Build a bridge from your legacy apps to the future.
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> _______________________________________________
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> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>

Re: [Iverilog-devel] system verilog syntax error.

[Lonnie L G. <lg...@sr...>]

I updated to a newer version of altera and got passed that and now back to the syntax errors in altera sv file errors. 

 

This is with the latest snap shot:  Icarus Verilog version 0.10.0 (devel) (s20140801)

 

Lonnie

 

/opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:1153: syntax error

/opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:1153: Syntax in assignment statement l-value.

/opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:1154: syntax error

/opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:1154: error: malformed statement

/opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:1155: syntax error

/opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:1155: error: malformed statement

/opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:1156: syntax error

/opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:1156: error: malformed statement

/opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:1157: syntax error

/opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:1157: error: malformed statement

/opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:1158: syntax error

/opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:1158: error: malformed statement

/opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:10676: syntax error

/opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:10673: error: Syntax error defining function.

 

        function [8*MAX_STRING_LENGTH-1:0] convert_to_mhz_string;

                input integer freq_value;

                input khz;

 

                integer n_mhz;

                integer fractional;

                const integer mega = 1000000;     ßline 1153

                integer actual_value;

                integer current_value, v1ghz, v100khz, threshold;

                reg [8*MAX_STRING_LENGTH-1:0] mhz_string;

                reg [8*MAX_STRING_LENGTH-1:0] f_mhz_string;

                integer digit, index, ii;

 

 

From: Iztok Jeras [mailto:izt...@gm...] 
Sent: Tuesday, August 05, 2014 8:35 AM
To: Discussions concerning Icarus Verilog development
Subject: Re: [Iverilog-devel] system verilog syntax error.

 

The source is not correct, this is what I get from ncsim:

$ irun soft.sv

irun: 14.10-p001: (c) Copyright 1995-2014 Cadence Design Systems, Inc.
file: soft.sv
module soft (in, out);
          |
ncvlog: *E,EXPMDN (soft.sv,2|10): expecting a module name.
    module worklib.???:sv
        errors: 1, warnings: 0
ncvlog: *F,NOTOPL: no top-level unit found, must have recursive instances.
irun: *E,VLGERR: An error occurred during parsing.  Review the log file for errors with the code *E and fix those identified problems to proceed.  Exiting with code (status 2).

The module name is a SystemVerilog reserved keyword, see standard:
1800-2012.pdf 18.5 Constraint blocks

I suggest you use syntax highlighting, to avoid reserved keywords.

 

Regards,

Iztok Jeras

 

On 5 August 2014 15:18, Lonnie L Gliem <lg...@sr...> wrote:

I updated to the latest snapshot and now I get this error which seems
strange?

Using language generation: IEEE1800-2012,no-specify,xtypes,icarus-misc
PARSING INPUT
/opt/altera12.1/quartus/eda/sim_lib/altera_primitives.v:83: syntax error
I give up.


`timescale 1 ps / 1 ps
module soft (in, out);    <-------- This is line 83.
    input in;
    output out;

    assign out = in;
endmodule

-----Original Message-----
From: Stephen Williams [mailto:st...@ic...]
Sent: Friday, August 01, 2014 4:43 PM
To: ive...@li...
Subject: Re: [Iverilog-devel] system verilog syntax error.

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1


I just tossed together a snapshot here:

<ftp://ftp.icarus.com/pub/eda/verilog/snapshots/verilog-20140801.tar.gz>

It's been a year since the last snapshot, so why the heck not?

There has also been talk of making a new 0.9 release, and possible talk of a
version 10 release as well, although the 0.9.8 would come first, since the
SystemVerilog work is still being furiously worked on.

On 08/01/2014 09:55 AM, Lonnie L Gliem wrote:
> I think I will just wait for the snapshot let me know when it is
> ready.
>
> Thanks Lonnie
>
>
> -----Original Message----- From: Stephen Williams
> [mailto:st...@ic...] Sent: Friday, August 01, 2014 11:27 AM
> To: ive...@li... Subject: Re:
> [Iverilog-devel] system verilog syntax error.
>
>
> You would need to extract it using "git". There is a detailed
> installation guide here, which includes a chapter on getting the
> source from git:
>
> <http://iverilog.wikia.com/wiki/Installation_Guide>
>
> Your request has pointed out an issue, that we really need to make a
> new snapshot. I'll see about doing that today.
>
>
> On 08/01/2014 09:22 AM, Lonnie L Gliem wrote:
>> Where do I find the git master branch?
>
>> -----Original Message----- From: Stephen Williams
>> [mailto:st...@ic...] Sent: Friday, August 01, 2014 11:20 AM
>> To: ive...@li... Subject: Re:
>> [Iverilog-devel] system verilog syntax error.
>
>
>> That snapshto is fairly old. I should make a new snapshot.
>> SystemVerilog support is in active development, the latest stuff is
>> in the git master branch.
>
>> On 08/01/2014 09:15 AM, Lonnie Gliem wrote:
>>> I tried the latest snapshot: Icarus Verilog version 0.10.0
>>> (devel) (s20130827)
>
>>> I get the following errors from this code in an altera system
>>> verilog file.
>
>>> Lonnie
>
>>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1360:
>>> syntax error
>>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1360:
>>> error: malformed statement
>>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1361:
>>> syntax error
>>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1361:
>>> error: malformed statement
>>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1362:
>>> syntax error
>>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1362:
>>> error: malformed statement
>>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1363:
>>> syntax error
>>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1363:
>>> error: malformed statement
>>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1364:
>>> syntax error
>>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1364:
>>> error: malformed statement
>
>>> altera .sv file
>
>>> //------------------------------------------------------------------
>>> -
>>>
>>>
- -
>>>
>>>
> ------
>
>
>> // Function Name    : strtobits
>>> // Description      : takes in a string where // each character
>>>  represents a hexadecimal number, transforms that number into //
>>> 4-bits, concatenates the result and returns it.
>>> //------------------------------------------------------------------
>>> -
>>>
>>>
- -
>>>
>>>
> ------
>
>>> function [4*MEM_INIT_STRING_LENGTH -1 : 0]  strtobits; input
>>> [8*MEM_INIT_STRING_LENGTH : 1] my_string; begin
>
>>> integer char_idx;  line 1361 integer bit_idx;        1362
>>> reg[7:0] my_char;       1363 reg[3:0] hex_value;     1364
>>> reg[4*MEM_INIT_STRING_LENGTH - 1 : 0] temp_bits;
>
>
>>> --------------------------------------------------------------------
>>> -
>>>
>>>
- -
>>>
>>>
> --------
>
>
>> Want fast and easy access to all the code in your enterprise?
>> Index and
>>> search up to 200,000 lines of code with a free copy of Black Duck
>>> Code Sight - the same software that powers the world's largest code
>>> search on Ohloh, the Black Duck Open Hub! Try it now.
>>> http://p.sf.net/sfu/bds
>>> _______________________________________________ Iverilog-devel
>>> mailing list Ive...@li...
>>> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>
>
>
>
>> ---------------------------------------------------------------------
>> -
>>
>>
- ------
>
>
> --
>> Want fast and easy access to all the code in your enterprise?
>> Index and search up to 200,000 lines of code with a free copy of
>> Black Duck Code Sight - the same software that powers the world's
>> largest code search on Ohloh, the Black Duck Open Hub! Try it now.
>> http://p.sf.net/sfu/bds
>> _______________________________________________ Iverilog-devel
>> mailing list Ive...@li...
>> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>
>
>
>> ---------------------------------------------------------------------
>> -
>>
>>
- --------
>
>
> Want fast and easy access to all the code in your enterprise? Index
> and
>> search up to 200,000 lines of code with a free copy of Black Duck
>> Code Sight - the same software that powers the world's largest code
>> search on Ohloh, the Black Duck Open Hub! Try it now.
>> http://p.sf.net/sfu/bds
>> _______________________________________________ Iverilog-devel
>> mailing list Ive...@li...
>> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>
>
>
> ----------------------------------------------------------------------
> ------
>
>
- --
> Want fast and easy access to all the code in your enterprise? Index
> and search up to 200,000 lines of code with a free copy of Black Duck
> Code Sight - the same software that powers the world's largest code
> search on Ohloh, the Black Duck Open Hub! Try it now.
> http://p.sf.net/sfu/bds
> _______________________________________________ Iverilog-devel mailing
> list Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>
>
>
> ----------------------------------------------------------------------
> --------
>
>
Want fast and easy access to all the code in your enterprise? Index and
> search up to 200,000 lines of code with a free copy of Black Duck Code
> Sight - the same software that powers the world's largest code search
> on Ohloh, the Black Duck Open Hub! Try it now.
> http://p.sf.net/sfu/bds
> _______________________________________________ Iverilog-devel mailing
> list Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>

- --
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.19 (GNU/Linux)
Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/

iEYEARECAAYFAlPcCeAACgkQrPt1Sc2b3inOHQCfQsnefYYkD/8OP4Di8nhhq3Ky
1pQAn2ML+75tBbcZTJc8F2xEWppgt8ro
=wiYa
-----END PGP SIGNATURE-----

----------------------------------------------------------------------------
--
Want fast and easy access to all the code in your enterprise? Index and
search up to 200,000 lines of code with a free copy of Black Duck
Code Sight - the same software that powers the world's largest code
search on Ohloh, the Black Duck Open Hub! Try it now.
http://p.sf.net/sfu/bds
_______________________________________________
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Re: [Iverilog-devel] system verilog syntax error.

[Cary R. <cy...@ya...>]

Icarus currently only handles constant class properties. To work around this try removing the const keyword in the function definition.
Cary 



On Tuesday, August 5, 2014 9:46 AM, Lonnie L Gliem <lg...@sr...> wrote:
 


I updated to a newer version of altera and got passed that and now back to the syntax errors in altera sv file errors. 
 
This is with the latest snap shot:  Icarus Verilog version 0.10.0 (devel) (s20140801)
 
Lonnie
 
/opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:1153: syntax error
/opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:1153: Syntax in assignment statement l-value.
/opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:1154: syntax error
/opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:1154: error: malformed statement
/opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:1155: syntax error
/opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:1155: error: malformed statement
/opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:1156: syntax error
/opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:1156: error: malformed statement
/opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:1157: syntax error
/opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:1157: error: malformed statement
/opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:1158: syntax error
/opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:1158: error: malformed statement
/opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:10676: syntax error
/opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:10673: error: Syntax error defining function.
 
        function [8*MAX_STRING_LENGTH-1:0] convert_to_mhz_string;
                input integer freq_value;
                input khz;
 
                integer n_mhz;
                integer fractional;
                const integer mega = 1000000;     ßline 1153
                integer actual_value;
                integer current_value, v1ghz, v100khz, threshold;
                reg [8*MAX_STRING_LENGTH-1:0] mhz_string;
                reg [8*MAX_STRING_LENGTH-1:0] f_mhz_string;
                integer digit, index, ii;
 
 _______________________________________________

Iverilog-devel mailing list
Ive...@li...
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Re: [Iverilog-devel] system verilog syntax error.

[Lonnie G. <lg...@sr...>]

Changed constant integer to integer and then it moved on to this error. 

/opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:10676: syntax error
/opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:10673: error: Syntax error defining function.

         `elsif GENERIC_PLL_TIMESCALE_1_US
		factor = factor / 10**9;

	`elsif GENERIC_PLL_TIMESCALE_10_US
		factor = factor /10**10;


On Tue, Aug 05, 2014 at 11:24:53AM -0700, Cary R. wrote:
> 
> 
> Icarus currently only handles constant class properties. To work around this try removing the const keyword in the function definition.
> Cary 
> 
> 
> 
> On Tuesday, August 5, 2014 9:46 AM, Lonnie L Gliem <lg...@sr...> wrote:
>  
> 
> 
> I updated to a newer version of altera and got passed that and now back to the syntax errors in altera sv file errors. 
>  
> This is with the latest snap shot:  Icarus Verilog version 0.10.0 (devel) (s20140801)
>  
> Lonnie
>  
> /opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:1153: syntax error
> /opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:1153: Syntax in assignment statement l-value.
> /opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:1154: syntax error
> /opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:1154: error: malformed statement
> /opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:1155: syntax error
> /opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:1155: error: malformed statement
> /opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:1156: syntax error
> /opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:1156: error: malformed statement
> /opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:1157: syntax error
> /opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:1157: error: malformed statement
> /opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:1158: syntax error
> /opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:1158: error: malformed statement
> /opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:10676: syntax error
> /opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:10673: error: Syntax error defining function.
>  
>         function [8*MAX_STRING_LENGTH-1:0] convert_to_mhz_string;
>                 input integer freq_value;
>                 input khz;
>  
>                 integer n_mhz;
>                 integer fractional;
>                 const integer mega = 1000000;     ßline 1153
>                 integer actual_value;
>                 integer current_value, v1ghz, v100khz, threshold;
>                 reg [8*MAX_STRING_LENGTH-1:0] mhz_string;
>                 reg [8*MAX_STRING_LENGTH-1:0] f_mhz_string;
>                 integer digit, index, ii;
>  
>  _______________________________________________
> 
> Iverilog-devel mailing list
> Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> ------------------------------------------------------------------------------
> Infragistics Professional
> Build stunning WinForms apps today!
> Reboot your WinForms applications with our WinForms controls. 
> Build a bridge from your legacy apps to the future.
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> _______________________________________________
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> Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel

Re: [Iverilog-devel] system verilog syntax error.

[Cary R. <cy...@ya...>]

That's not enough context to figure out the problem and you didn't specify exactly which line was causing the problem.

Cary



On Tuesday, August 5, 2014 1:19 PM, Lonnie Gliem <lg...@sr...> wrote:
 


Changed constant integer to integer and then it moved on to this error. 

/opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:10676: syntax error
/opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:10673: error: Syntax error defining function.

         `elsif GENERIC_PLL_TIMESCALE_1_US
        factor = factor / 10**9;

    `elsif GENERIC_PLL_TIMESCALE_10_US
        factor = factor /10**10;


On Tue, Aug 05, 2014 at 11:24:53AM -0700, Cary R. wrote:
> 
> 
> Icarus currently only handles constant class properties. To work around this try removing the const keyword in the function definition.
> Cary 
> 
> 
> 
> On Tuesday, August 5, 2014 9:46 AM, Lonnie L Gliem <lg...@sr...> wrote:
>  
> 
> 
> I updated to a newer version of altera and got passed that and now back to the syntax errors in altera sv file errors. 
>  
> This is with the latest snap shot:  Icarus Verilog version 0.10.0 (devel) (s20140801)
>  
> Lonnie
>  
> /opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:1153: syntax error
> /opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:1153: Syntax in assignment statement l-value.
> /opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:1154: syntax error
> /opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:1154: error: malformed statement
> /opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:1155: syntax error
> /opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:1155: error: malformed statement
> /opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:1156: syntax error
> /opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:1156: error: malformed statement
> /opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:1157: syntax error
> /opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:1157: error: malformed statement
> /opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:1158: syntax error
> /opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:1158: error: malformed statement
> /opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:10676: syntax error
> /opt/altera13.0/quartus/eda/sim_lib/altera_lnsim.sv:10673: error: Syntax error defining function.
>  
>         function [8*MAX_STRING_LENGTH-1:0] convert_to_mhz_string;
>                 input integer freq_value;
>                 input khz;
>  
>                 integer n_mhz;
>                 integer fractional;
>                 const integer mega = 1000000;     ßline 1153
>                 integer actual_value;
>                 integer current_value, v1ghz, v100khz, threshold;
>                 reg [8*MAX_STRING_LENGTH-1:0] mhz_string;
>                 reg [8*MAX_STRING_LENGTH-1:0] f_mhz_string;
>                 integer digit, index, ii;
>  
>  _______________________________________________
> 
> Iverilog-devel mailing list
> Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> ------------------------------------------------------------------------------
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> Build stunning WinForms apps today!
> Reboot your WinForms applications with our WinForms controls. 
> Build a bridge from your legacy apps to the future.
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> _______________________________________________
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Re: [Iverilog-devel] system verilog syntax error.

[Lonnie G. <lg...@sr...>]

That's weird I use G-2012 vcsmx and it compiles it without error.

I am not familiar with syntax highlighting can you elaborate.

On Aug 5, 2014, at 8:34 AM, Iztok Jeras <izt...@gm...> wrote:

> The source is not correct, this is what I get from ncsim:
> 
> $ irun soft.sv
> irun: 14.10-p001: (c) Copyright 1995-2014 Cadence Design Systems, Inc.
> file: soft.sv
> module soft (in, out);
>           |
> ncvlog: *E,EXPMDN (soft.sv,2|10): expecting a module name.
>     module worklib.???:sv
>         errors: 1, warnings: 0
> ncvlog: *F,NOTOPL: no top-level unit found, must have recursive instances.
> irun: *E,VLGERR: An error occurred during parsing.  Review the log file for errors with the code *E and fix those identified problems to proceed.  Exiting with code (status 2).
> 
> The module name is a SystemVerilog reserved keyword, see standard:
> 1800-2012.pdf 18.5 Constraint blocks
> I suggest you use syntax highlighting, to avoid reserved keywords.
> 
> Regards,
> Iztok Jeras
> 
> 
> On 5 August 2014 15:18, Lonnie L Gliem <lg...@sr...> wrote:
> I updated to the latest snapshot and now I get this error which seems
> strange?
> 
> Using language generation: IEEE1800-2012,no-specify,xtypes,icarus-misc
> PARSING INPUT
> /opt/altera12.1/quartus/eda/sim_lib/altera_primitives.v:83: syntax error
> I give up.
> 
> 
> `timescale 1 ps / 1 ps
> module soft (in, out);    <-------- This is line 83.
>     input in;
>     output out;
> 
>     assign out = in;
> endmodule
> 
> -----Original Message-----
> From: Stephen Williams [mailto:st...@ic...]
> Sent: Friday, August 01, 2014 4:43 PM
> To: ive...@li...
> Subject: Re: [Iverilog-devel] system verilog syntax error.
> 
> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA1
> 
> 
> I just tossed together a snapshot here:
> 
> <ftp://ftp.icarus.com/pub/eda/verilog/snapshots/verilog-20140801.tar.gz>
> 
> It's been a year since the last snapshot, so why the heck not?
> 
> There has also been talk of making a new 0.9 release, and possible talk of a
> version 10 release as well, although the 0.9.8 would come first, since the
> SystemVerilog work is still being furiously worked on.
> 
> On 08/01/2014 09:55 AM, Lonnie L Gliem wrote:
> > I think I will just wait for the snapshot let me know when it is
> > ready.
> >
> > Thanks Lonnie
> >
> >
> > -----Original Message----- From: Stephen Williams
> > [mailto:st...@ic...] Sent: Friday, August 01, 2014 11:27 AM
> > To: ive...@li... Subject: Re:
> > [Iverilog-devel] system verilog syntax error.
> >
> >
> > You would need to extract it using "git". There is a detailed
> > installation guide here, which includes a chapter on getting the
> > source from git:
> >
> > <http://iverilog.wikia.com/wiki/Installation_Guide>
> >
> > Your request has pointed out an issue, that we really need to make a
> > new snapshot. I'll see about doing that today.
> >
> >
> > On 08/01/2014 09:22 AM, Lonnie L Gliem wrote:
> >> Where do I find the git master branch?
> >
> >> -----Original Message----- From: Stephen Williams
> >> [mailto:st...@ic...] Sent: Friday, August 01, 2014 11:20 AM
> >> To: ive...@li... Subject: Re:
> >> [Iverilog-devel] system verilog syntax error.
> >
> >
> >> That snapshto is fairly old. I should make a new snapshot.
> >> SystemVerilog support is in active development, the latest stuff is
> >> in the git master branch.
> >
> >> On 08/01/2014 09:15 AM, Lonnie Gliem wrote:
> >>> I tried the latest snapshot: Icarus Verilog version 0.10.0
> >>> (devel) (s20130827)
> >
> >>> I get the following errors from this code in an altera system
> >>> verilog file.
> >
> >>> Lonnie
> >
> >>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1360:
> >>> syntax error
> >>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1360:
> >>> error: malformed statement
> >>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1361:
> >>> syntax error
> >>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1361:
> >>> error: malformed statement
> >>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1362:
> >>> syntax error
> >>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1362:
> >>> error: malformed statement
> >>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1363:
> >>> syntax error
> >>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1363:
> >>> error: malformed statement
> >>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1364:
> >>> syntax error
> >>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1364:
> >>> error: malformed statement
> >
> >>> altera .sv file
> >
> >>> //------------------------------------------------------------------
> >>> -
> >>>
> >>>
> - -
> >>>
> >>>
> > ------
> >
> >
> >> // Function Name    : strtobits
> >>> // Description      : takes in a string where // each character
> >>>  represents a hexadecimal number, transforms that number into //
> >>> 4-bits, concatenates the result and returns it.
> >>> //------------------------------------------------------------------
> >>> -
> >>>
> >>>
> - -
> >>>
> >>>
> > ------
> >
> >>> function [4*MEM_INIT_STRING_LENGTH -1 : 0]  strtobits; input
> >>> [8*MEM_INIT_STRING_LENGTH : 1] my_string; begin
> >
> >>> integer char_idx;  line 1361 integer bit_idx;        1362
> >>> reg[7:0] my_char;       1363 reg[3:0] hex_value;     1364
> >>> reg[4*MEM_INIT_STRING_LENGTH - 1 : 0] temp_bits;
> >
> >
> >>> --------------------------------------------------------------------
> >>> -
> >>>
> >>>
> - -
> >>>
> >>>
> > --------
> >
> >
> >> Want fast and easy access to all the code in your enterprise?
> >> Index and
> >>> search up to 200,000 lines of code with a free copy of Black Duck
> >>> Code Sight - the same software that powers the world's largest code
> >>> search on Ohloh, the Black Duck Open Hub! Try it now.
> >>> http://p.sf.net/sfu/bds
> >>> _______________________________________________ Iverilog-devel
> >>> mailing list Ive...@li...
> >>> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> >
> >
> >
> >
> >> ---------------------------------------------------------------------
> >> -
> >>
> >>
> - ------
> >
> >
> > --
> >> Want fast and easy access to all the code in your enterprise?
> >> Index and search up to 200,000 lines of code with a free copy of
> >> Black Duck Code Sight - the same software that powers the world's
> >> largest code search on Ohloh, the Black Duck Open Hub! Try it now.
> >> http://p.sf.net/sfu/bds
> >> _______________________________________________ Iverilog-devel
> >> mailing list Ive...@li...
> >> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> >
> >
> >
> >> ---------------------------------------------------------------------
> >> -
> >>
> >>
> - --------
> >
> >
> > Want fast and easy access to all the code in your enterprise? Index
> > and
> >> search up to 200,000 lines of code with a free copy of Black Duck
> >> Code Sight - the same software that powers the world's largest code
> >> search on Ohloh, the Black Duck Open Hub! Try it now.
> >> http://p.sf.net/sfu/bds
> >> _______________________________________________ Iverilog-devel
> >> mailing list Ive...@li...
> >> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> >
> >
> >
> > ----------------------------------------------------------------------
> > ------
> >
> >
> - --
> > Want fast and easy access to all the code in your enterprise? Index
> > and search up to 200,000 lines of code with a free copy of Black Duck
> > Code Sight - the same software that powers the world's largest code
> > search on Ohloh, the Black Duck Open Hub! Try it now.
> > http://p.sf.net/sfu/bds
> > _______________________________________________ Iverilog-devel mailing
> > list Ive...@li...
> > https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> >
> >
> >
> > ----------------------------------------------------------------------
> > --------
> >
> >
> Want fast and easy access to all the code in your enterprise? Index and
> > search up to 200,000 lines of code with a free copy of Black Duck Code
> > Sight - the same software that powers the world's largest code search
> > on Ohloh, the Black Duck Open Hub! Try it now.
> > http://p.sf.net/sfu/bds
> > _______________________________________________ Iverilog-devel mailing
> > list Ive...@li...
> > https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> >
> 
> - --
> Steve Williams                "The woods are lovely, dark and deep.
> steve at icarus.com           But I have promises to keep,
> http://www.icarus.com         and lines to code before I sleep,
> http://www.picturel.com       And lines to code before I sleep."
> -----BEGIN PGP SIGNATURE-----
> Version: GnuPG v2.0.19 (GNU/Linux)
> Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/
> 
> iEYEARECAAYFAlPcCeAACgkQrPt1Sc2b3inOHQCfQsnefYYkD/8OP4Di8nhhq3Ky
> 1pQAn2ML+75tBbcZTJc8F2xEWppgt8ro
> =wiYa
> -----END PGP SIGNATURE-----
> 
> ----------------------------------------------------------------------------
> --
> Want fast and easy access to all the code in your enterprise? Index and
> search up to 200,000 lines of code with a free copy of Black Duck
> Code Sight - the same software that powers the world's largest code
> search on Ohloh, the Black Duck Open Hub! Try it now.
> http://p.sf.net/sfu/bds
> _______________________________________________
> Iverilog-devel mailing list
> Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> 
> 
> 
> ------------------------------------------------------------------------------
> Infragistics Professional
> Build stunning WinForms apps today!
> Reboot your WinForms applications with our WinForms controls.
> Build a bridge from your legacy apps to the future.
> http://pubads.g.doubleclick.net/gampad/clk?id=153845071&iu=/4140/ostg.clktrk
> _______________________________________________
> Iverilog-devel mailing list
> Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
> 
> <soft.sv>
> ------------------------------------------------------------------------------
> Infragistics Professional
> Build stunning WinForms apps today!
> Reboot your WinForms applications with our WinForms controls. 
> Build a bridge from your legacy apps to the future.
> http://pubads.g.doubleclick.net/gampad/clk?id=153845071&iu=/4140/ostg.clktrk
> _______________________________________________
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> Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel

Re: [Iverilog-devel] system verilog syntax error.

[Iztok J. <izt...@gm...>]

Hi Lonnie,

Using an editor which understands the SystemVerilog language, I use VI and
this:
https://github.com/nachumk/systemverilog.vim

Regards,
Iztok Jeras



On 5 August 2014 16:03, Lonnie Gliem <lg...@sr...> wrote:

> That's weird I use G-2012 vcsmx and it compiles it without error.
>
> I am not familiar with syntax highlighting can you elaborate.
>
> On Aug 5, 2014, at 8:34 AM, Iztok Jeras <izt...@gm...> wrote:
>
> The source is not correct, this is what I get from ncsim:
>
> $ irun soft.sv
> irun: 14.10-p001: (c) Copyright 1995-2014 Cadence Design Systems, Inc.
> file: soft.sv
> module soft (in, out);
>           |
> ncvlog: *E,EXPMDN (soft.sv,2|10): expecting a module name.
>     module worklib.???:sv
>         errors: 1, warnings: 0
> ncvlog: *F,NOTOPL: no top-level unit found, must have recursive instances.
> irun: *E,VLGERR: An error occurred during parsing.  Review the log file
> for errors with the code *E and fix those identified problems to proceed.
> Exiting with code (status 2).
>
> The module name is a SystemVerilog reserved keyword, see standard:
> 1800-2012.pdf 18.5 Constraint blocks
> I suggest you use syntax highlighting, to avoid reserved keywords.
>
> Regards,
> Iztok Jeras
>
>
> On 5 August 2014 15:18, Lonnie L Gliem < <lg...@sr...>
> lg...@sr...> wrote:
>
>> I updated to the latest snapshot and now I get this error which seems
>> strange?
>>
>> Using language generation: IEEE1800-2012,no-specify,xtypes,icarus-misc
>> PARSING INPUT
>> /opt/altera12.1/quartus/eda/sim_lib/altera_primitives.v:83: syntax error
>> I give up.
>>
>>
>> `timescale 1 ps / 1 ps
>> module soft (in, out);    <-------- This is line 83.
>>     input in;
>>     output out;
>>
>>     assign out = in;
>> endmodule
>>
>> -----Original Message-----
>> From: Stephen Williams [mailto: <st...@ic...>st...@ic...]
>> Sent: Friday, August 01, 2014 4:43 PM
>> To: <ive...@li...>
>> ive...@li...
>> Subject: Re: [Iverilog-devel] system verilog syntax error.
>>
>> -----BEGIN PGP SIGNED MESSAGE-----
>> Hash: SHA1
>>
>>
>> I just tossed together a snapshot here:
>>
>> <
>> <ftp://ftp.icarus.com/pub/eda/verilog/snapshots/verilog-20140801.tar.gz>
>> ftp://ftp.icarus.com/pub/eda/verilog/snapshots/verilog-20140801.tar.gz>
>>
>> It's been a year since the last snapshot, so why the heck not?
>>
>> There has also been talk of making a new 0.9 release, and possible talk
>> of a
>> version 10 release as well, although the 0.9.8 would come first, since the
>> SystemVerilog work is still being furiously worked on.
>>
>> On 08/01/2014 09:55 AM, Lonnie L Gliem wrote:
>> > I think I will just wait for the snapshot let me know when it is
>> > ready.
>> >
>> > Thanks Lonnie
>> >
>> >
>> > -----Original Message----- From: Stephen Williams
>> > [mailto: <st...@ic...>st...@ic...] Sent: Friday, August 01,
>> 2014 11:27 AM
>> > To: <ive...@li...>
>> ive...@li... Subject: Re:
>> > [Iverilog-devel] system verilog syntax error.
>> >
>> >
>> > You would need to extract it using "git". There is a detailed
>> > installation guide here, which includes a chapter on getting the
>> > source from git:
>> >
>> > < <http://iverilog.wikia.com/wiki/Installation_Guide>
>> http://iverilog.wikia.com/wiki/Installation_Guide>
>> >
>> > Your request has pointed out an issue, that we really need to make a
>> > new snapshot. I'll see about doing that today.
>> >
>> >
>> > On 08/01/2014 09:22 AM, Lonnie L Gliem wrote:
>> >> Where do I find the git master branch?
>> >
>> >> -----Original Message----- From: Stephen Williams
>> >> [mailto: <st...@ic...>st...@ic...] Sent: Friday, August 01,
>> 2014 11:20 AM
>> >> To: <ive...@li...>
>> ive...@li... Subject: Re:
>> >> [Iverilog-devel] system verilog syntax error.
>> >
>> >
>> >> That snapshto is fairly old. I should make a new snapshot.
>> >> SystemVerilog support is in active development, the latest stuff is
>> >> in the git master branch.
>> >
>> >> On 08/01/2014 09:15 AM, Lonnie Gliem wrote:
>> >>> I tried the latest snapshot: Icarus Verilog version 0.10.0
>> >>> (devel) (s20130827)
>> >
>> >>> I get the following errors from this code in an altera system
>> >>> verilog file.
>> >
>> >>> Lonnie
>> >
>> >>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1360:
>> >>> syntax error
>> >>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1360:
>> >>> error: malformed statement
>> >>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1361:
>> >>> syntax error
>> >>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1361:
>> >>> error: malformed statement
>> >>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1362:
>> >>> syntax error
>> >>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1362:
>> >>> error: malformed statement
>> >>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1363:
>> >>> syntax error
>> >>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1363:
>> >>> error: malformed statement
>> >>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1364:
>> >>> syntax error
>> >>> /opt/altera12.1/quartus/eda/sim_lib/altera_lnsim.sv:1364:
>> >>> error: malformed statement
>> >
>> >>> altera .sv file
>> >
>> >>> //------------------------------------------------------------------
>> >>> -
>> >>>
>> >>>
>> - -
>> >>>
>> >>>
>> > ------
>> >
>> >
>> >> // Function Name    : strtobits
>> >>> // Description      : takes in a string where // each character
>> >>>  represents a hexadecimal number, transforms that number into //
>> >>> 4-bits, concatenates the result and returns it.
>> >>> //------------------------------------------------------------------
>> >>> -
>> >>>
>> >>>
>> - -
>> >>>
>> >>>
>> > ------
>> >
>> >>> function [4*MEM_INIT_STRING_LENGTH -1 : 0]  strtobits; input
>> >>> [8*MEM_INIT_STRING_LENGTH : 1] my_string; begin
>> >
>> >>> integer char_idx;  line 1361 integer bit_idx;        1362
>> >>> reg[7:0] my_char;       1363 reg[3:0] hex_value;     1364
>> >>> reg[4*MEM_INIT_STRING_LENGTH - 1 : 0] temp_bits;
>> >
>> >
>> >>> --------------------------------------------------------------------
>> >>> -
>> >>>
>> >>>
>> - -
>> >>>
>> >>>
>> > --------
>> >
>> >
>> >> Want fast and easy access to all the code in your enterprise?
>> >> Index and
>> >>> search up to 200,000 lines of code with a free copy of Black Duck
>> >>> Code Sight - the same software that powers the world's largest code
>> >>> search on Ohloh, the Black Duck Open Hub! Try it now.
>> >>> <http://p.sf.net/sfu/bds>http://p.sf.net/sfu/bds
>> >>> _______________________________________________ Iverilog-devel
>> >>> mailing list <Ive...@li...>
>> Ive...@li...
>> >>> <https://lists.sourceforge.net/lists/listinfo/iverilog-devel>
>> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>> >
>> >
>> >
>> >
>> >> ---------------------------------------------------------------------
>> >> -
>> >>
>> >>
>> - ------
>> >
>> >
>> > --
>> >> Want fast and easy access to all the code in your enterprise?
>> >> Index and search up to 200,000 lines of code with a free copy of
>> >> Black Duck Code Sight - the same software that powers the world's
>> >> largest code search on Ohloh, the Black Duck Open Hub! Try it now.
>> >> <http://p.sf.net/sfu/bds>http://p.sf.net/sfu/bds
>> >> _______________________________________________ Iverilog-devel
>> >> mailing list <Ive...@li...>
>> Ive...@li...
>> >> <https://lists.sourceforge.net/lists/listinfo/iverilog-devel>
>> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>> >
>> >
>> >
>> >> ---------------------------------------------------------------------
>> >> -
>> >>
>> >>
>> - --------
>> >
>> >
>> > Want fast and easy access to all the code in your enterprise? Index
>> > and
>> >> search up to 200,000 lines of code with a free copy of Black Duck
>> >> Code Sight - the same software that powers the world's largest code
>> >> search on Ohloh, the Black Duck Open Hub! Try it now.
>> >> <http://p.sf.net/sfu/bds>http://p.sf.net/sfu/bds
>> >> _______________________________________________ Iverilog-devel
>> >> mailing list <Ive...@li...>
>> Ive...@li...
>> >> <https://lists.sourceforge.net/lists/listinfo/iverilog-devel>
>> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>> >
>> >
>> >
>> > ----------------------------------------------------------------------
>> > ------
>> >
>> >
>> - --
>> > Want fast and easy access to all the code in your enterprise? Index
>> > and search up to 200,000 lines of code with a free copy of Black Duck
>> > Code Sight - the same software that powers the world's largest code
>> > search on Ohloh, the Black Duck Open Hub! Try it now.
>> > <http://p.sf.net/sfu/bds>http://p.sf.net/sfu/bds
>> > _______________________________________________ Iverilog-devel mailing
>> > list <Ive...@li...>
>> Ive...@li...
>> > <https://lists.sourceforge.net/lists/listinfo/iverilog-devel>
>> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>> >
>> >
>> >
>> > ----------------------------------------------------------------------
>> > --------
>> >
>> >
>> Want fast and easy access to all the code in your enterprise? Index and
>> > search up to 200,000 lines of code with a free copy of Black Duck Code
>> > Sight - the same software that powers the world's largest code search
>> > on Ohloh, the Black Duck Open Hub! Try it now.
>> > <http://p.sf.net/sfu/bds>http://p.sf.net/sfu/bds
>> > _______________________________________________ Iverilog-devel mailing
>> > list <Ive...@li...>
>> Ive...@li...
>> > <https://lists.sourceforge.net/lists/listinfo/iverilog-devel>
>> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>> >
>>
>> - --
>> Steve Williams                "The woods are lovely, dark and deep.
>> steve at <http://icarus.com>icarus.com           But I have promises to
>> keep,
>>  <http://www.icarus.com>http://www.icarus.com         and lines to code
>> before I sleep,
>>  <http://www.picturel.com>http://www.picturel.com       And lines to
>> code before I sleep."
>> -----BEGIN PGP SIGNATURE-----
>> Version: GnuPG v2.0.19 (GNU/Linux)
>> Comment: Using GnuPG with Thunderbird - <http://www.enigmail.net/>
>> http://www.enigmail.net/
>>
>> iEYEARECAAYFAlPcCeAACgkQrPt1Sc2b3inOHQCfQsnefYYkD/8OP4Di8nhhq3Ky
>> 1pQAn2ML+75tBbcZTJc8F2xEWppgt8ro
>> =wiYa
>> -----END PGP SIGNATURE-----
>>
>>
>> ----------------------------------------------------------------------------
>> --
>> Want fast and easy access to all the code in your enterprise? Index and
>> search up to 200,000 lines of code with a free copy of Black Duck
>> Code Sight - the same software that powers the world's largest code
>> search on Ohloh, the Black Duck Open Hub! Try it now.
>>  <http://p.sf.net/sfu/bds>http://p.sf.net/sfu/bds
>> _______________________________________________
>> Iverilog-devel mailing list
>>  <Ive...@li...>
>> Ive...@li...
>>  <https://lists.sourceforge.net/lists/listinfo/iverilog-devel>
>> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>>
>>
>>
>>
>> ------------------------------------------------------------------------------
>> Infragistics Professional
>> Build stunning WinForms apps today!
>> Reboot your WinForms applications with our WinForms controls.
>> Build a bridge from your legacy apps to the future.
>>
>> <http://pubads.g.doubleclick.net/gampad/clk?id=153845071&iu=/4140/ostg.clktrk>
>> http://pubads.g.doubleclick.net/gampad/clk?id=153845071&iu=/4140/ostg.clktrk
>> _______________________________________________
>> Iverilog-devel mailing list
>>  <Ive...@li...>
>> Ive...@li...
>>  <https://lists.sourceforge.net/lists/listinfo/iverilog-devel>
>> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>>
>
> <soft.sv>
>
>
> ------------------------------------------------------------------------------
> Infragistics Professional
> Build stunning WinForms apps today!
> Reboot your WinForms applications with our WinForms controls.
> Build a bridge from your legacy apps to the future.
>
> http://pubads.g.doubleclick.net/gampad/clk?id=153845071&iu=/4140/ostg.clktrk
>
> _______________________________________________
> Iverilog-devel mailing list
> Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>
>
>
> ------------------------------------------------------------------------------
> Infragistics Professional
> Build stunning WinForms apps today!
> Reboot your WinForms applications with our WinForms controls.
> Build a bridge from your legacy apps to the future.
>
> http://pubads.g.doubleclick.net/gampad/clk?id=153845071&iu=/4140/ostg.clktrk
> _______________________________________________
> Iverilog-devel mailing list
> Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>
>