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From: Cary R. <cy...@ya...> - 2015-01-28 21:21:58
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Hi Lonnie,
It did appear multiple times. I believe the list software does not send you a copy, but if you look in the archives it is usually there.
The issue you are experiencing is that somehow a value is being put to a signal and the width of the value does not match the width of the signal. You may be able to get some information to narrow this down by printing the various state information before the assert() (e.g. the actual current and new bit values/size, etc.). That should allow you to then try to debug this down to a specific piece of Verilog code. This can often be fairly convoluted (e.g. a signal passed to a port with a specific type of driver, etc.), so it's not always easy to create a small/simple example.
I can help you off list if needed, but without the source code you are going to need to do most of the basic debug work.
Have you tried this with other version to see if this is just a problem in that snapshot?
These problems are often a bug in the code generated by the compiler for corner cases that are not handled correctly.
Cary
On Wednesday, January 28, 2015 12:45 PM, Lonnie L Gliem <lg...@sr...> wrote:
<!--#yiv0649106253 _filtered #yiv0649106253 {font-family:Calibri;panose-1:2 15 5 2 2 2 4 3 2 4;} _filtered #yiv0649106253 {font-family:Tahoma;panose-1:2 11 6 4 3 5 4 4 2 4;}#yiv0649106253 #yiv0649106253 p.yiv0649106253MsoNormal, #yiv0649106253 li.yiv0649106253MsoNormal, #yiv0649106253 div.yiv0649106253MsoNormal {margin:0in;margin-bottom:.0001pt;font-size:11.0pt;font-family:"Calibri", "sans-serif";}#yiv0649106253 a:link, #yiv0649106253 span.yiv0649106253MsoHyperlink {color:blue;text-decoration:underline;}#yiv0649106253 a:visited, #yiv0649106253 span.yiv0649106253MsoHyperlinkFollowed {color:purple;text-decoration:underline;}#yiv0649106253 span.yiv0649106253EmailStyle17 {font-family:"Calibri", "sans-serif";color:windowtext;}#yiv0649106253 span.yiv0649106253EmailStyle18 {font-family:"Calibri", "sans-serif";color:#1F497D;}#yiv0649106253 .yiv0649106253MsoChpDefault {font-size:10.0pt;} _filtered #yiv0649106253 {margin:1.0in 1.0in 1.0in 1.0in;}#yiv0649106253 div.yiv0649106253WordSection1 {}-->Hi Cary,I tried posting this to the iverilog devel list but I don’t think it’s working so thought I would try sending it direct to you. ThanksLonnie From: Lonnie L Gliem [mailto:lg...@sr...]
Sent: Wednesday, January 28, 2015 2:21 PM
To: 'ive...@li...'
Subject: vvp runtime error Sorry if this is a multiple posting but I never saw the last one.I started getting a runtime error with 20150105 snapshot. Can someone tell me how to get more info on what it is blowing up on. Here is the error. -v: vvp_net_sig.cc:181: virtual void vvp_fun_signal4_sa::recv_vec4(vvp_net_ptr_t, const vvp_vector4_t&, void**): Assertion `bit.size() == bits4_.size()' failed.
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From: Lonnie G. <lg...@sr...> - 2015-02-02 17:03:55
Attachments:
iverilog_core.v
|
Hi Cary, I found the code causing the error and have attahced a small verilog file that causes it. iverilog iverilog_core.v Then run it. [lgliem@ajax ulogic_sim]$ ./a.out Fun: 0x7ba500 is for variable clk Fun: 0x7ba550 is for variable data_in_tmp Current vector is:32'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX New value is:33'bZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ vvp: vvp_net_sig.cc:185: virtual void vvp_fun_signal4_sa::recv_vec4(vvp_net_ptr_t, const vvp_vector4_t&, void**): Assertion `bit.size() == bits4_.size()' failed. Aborted (core dumped) Lonnie |
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From: Cary R. <cy...@ya...> - 2015-02-02 18:20:42
|
Hi Lonnie,
I was able to reduce this example down even further. It looks like the problem is that when Steve switched to the new stack code something broke concerning zero replications. At the moment an input width of 32 is getting a sign bit added which gives a width of 33 instead of 32. I will try to look at this later today.
Cary
On Monday, February 2, 2015 9:03 AM, Lonnie Gliem <lg...@sr...> wrote:
Hi Cary,
I found the code causing the error and have attahced a small verilog
file that causes it.
iverilog iverilog_core.v
Then run it.
[lgliem@ajax ulogic_sim]$ ./a.out
Fun: 0x7ba500 is for variable clk
Fun: 0x7ba550 is for variable data_in_tmp
Current vector is:32'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
New value is:33'bZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ
vvp: vvp_net_sig.cc:185: virtual void
vvp_fun_signal4_sa::recv_vec4(vvp_net_ptr_t, const vvp_vector4_t&,
void**): Assertion `bit.size() == bits4_.size()' failed.
Aborted (core dumped)
Lonnie
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From: Cary R. <cy...@ya...> - 2015-02-02 23:43:47
|
A patch for this has been pushed to git.
The issues was that zero replications inside of concatenations were generating incorrect vvp code for the new stack based vector operators. For the moment this code checks to see if the sub-expression width is zero. A more specific fix would check to see if the sub-expression was a concatenation that had a zero replication. I can easily change the code if needed, but the zero width may be better if other things can also generate a zero width result. I don't know of any, but there may be SystemVerilog constructs that can do this. Does anyone have an opinion on this or know of a construct that can do this?
Cary
On Monday, February 2, 2015 10:20 AM, Cary R. <cy...@ya...> wrote:
Hi Lonnie,
I was able to reduce this example down even further. It looks like the problem is that when Steve switched to the new stack code something broke concerning zero replications. At the moment an input width of 32 is getting a sign bit added which gives a width of 33 instead of 32. I will try to look at this later today.
Cary
On Monday, February 2, 2015 9:03 AM, Lonnie Gliem <lg...@sr...> wrote:
Hi Cary,
I found the code causing the error and have attahced a small verilog
file that causes it.
iverilog iverilog_core.v
Then run it.
[lgliem@ajax ulogic_sim]$ ./a.out
Fun: 0x7ba500 is for variable clk
Fun: 0x7ba550 is for variable data_in_tmp
Current vector is:32'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
New value is:33'bZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ
vvp: vvp_net_sig.cc:185: virtual void
vvp_fun_signal4_sa::recv_vec4(vvp_net_ptr_t, const vvp_vector4_t&,
void**): Assertion `bit.size() == bits4_.size()' failed.
Aborted (core dumped)
Lonnie
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From: Stephen W. <st...@ic...> - 2015-02-02 23:59:40
|
-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 I kinda think this should be restricted to zero-replications, and NOT zero-width expressions in general. I would rather catch the latter is an error, or something. On 02/02/2015 03:43 PM, Cary R. wrote: > A patch for this has been pushed to git. > > The issues was that zero replications inside of concatenations > were generating incorrect vvp code for the new stack based vector > operators. For the moment this code checks to see if the > sub-expression width is zero. A more specific fix would check to > see if the sub-expression was a concatenation that had a zero > replication. I can easily change the code if needed, but the zero > width may be better if other things can also generate a zero width > result. I don't know of any, but there may be SystemVerilog > constructs that can do this. Does anyone have an opinion on this or > know of a construct that can do this? > > Cary > > > On Monday, February 2, 2015 10:20 AM, Cary R. <cy...@ya...> > wrote: > > > Hi Lonnie, > > I was able to reduce this example down even further. It looks like > the problem is that when Steve switched to the new stack code > something broke concerning zero replications. At the moment an > input width of 32 is getting a sign bit added which gives a width > of 33 instead of 32. I will try to look at this later today. > > Cary > > > On Monday, February 2, 2015 9:03 AM, Lonnie Gliem > <lg...@sr...> wrote: > > > Hi Cary, I found the code causing the error and have attahced a > small verilog file that causes it. > > iverilog iverilog_core.v > > Then run it. [lgliem@ajax <mailto:lgliem@ajax> ulogic_sim]$ > ./a.out Fun: 0x7ba500 is for variable clk Fun: 0x7ba550 is for > variable data_in_tmp Current vector > is:32'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX New value > is:33'bZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ vvp: vvp_net_sig.cc:185: > virtual void vvp_fun_signal4_sa::recv_vec4(vvp_net_ptr_t, const > vvp_vector4_t&, void**): Assertion `bit.size() == bits4_.size()' > failed. Aborted (core dumped) > > Lonnie > > > > > > > > ------------------------------------------------------------------------------ > > Dive into the World of Parallel Programming. The Go Parallel Website, > sponsored by Intel and developed in partnership with Slashdot > Media, is your hub for all things parallel software development, > from weekly thought leadership blogs to news, videos, case studies, > tutorials and more. Take a look and join the conversation now. > http://goparallel.sourceforge.net/ > > > > _______________________________________________ Iverilog-devel > mailing list Ive...@li... > https://lists.sourceforge.net/lists/listinfo/iverilog-devel > - -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep." -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iEYEARECAAYFAlTQD18ACgkQrPt1Sc2b3inRWwCgtO8bBl+odSjaLxrskLw62HWU F+8AoOuTKqoQMRyYVpPDtm7JD8yYYVrF =qK5u -----END PGP SIGNATURE----- |
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From: Cary R. <cy...@ya...> - 2015-02-03 00:26:53
|
Okay, there are still a few other issues since nested replications do not correctly check for a zero replication at a lower level which was why I thought I may have to keep the zero width check. (e.g. {{2{{0{sign}}}}, 16'h0001} should report that a zero width (zero replication) cannot be replicated. A zero replication is only allowed in a concatenation/replication if it is also included with another non-zero width element. There are likely other degenerate cases (e.g. {{0{sign}}, {0{lsb}}}, etc.) that need to be checked and reported in the compiler.
And then all this needs to be check for constant and non-constant values being replicated. Constant-constant is done in the compiler, constant-variable is done in the run time.
Cary
On Monday, February 2, 2015 4:00 PM, Stephen Williams <st...@ic...> wrote:
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
I kinda think this should be restricted to zero-replications,
and NOT zero-width expressions in general. I would rather catch
the latter is an error, or something.
On 02/02/2015 03:43 PM, Cary R. wrote:
> A patch for this has been pushed to git.
>
> The issues was that zero replications inside of concatenations
> were generating incorrect vvp code for the new stack based vector
> operators. For the moment this code checks to see if the
> sub-expression width is zero. A more specific fix would check to
> see if the sub-expression was a concatenation that had a zero
> replication. I can easily change the code if needed, but the zero
> width may be better if other things can also generate a zero width
> result. I don't know of any, but there may be SystemVerilog
> constructs that can do this. Does anyone have an opinion on this or
> know of a construct that can do this?
>
> Cary
>
>
> On Monday, February 2, 2015 10:20 AM, Cary R. <cy...@ya...>
> wrote:
>
>
> Hi Lonnie,
>
> I was able to reduce this example down even further. It looks like
> the problem is that when Steve switched to the new stack code
> something broke concerning zero replications. At the moment an
> input width of 32 is getting a sign bit added which gives a width
> of 33 instead of 32. I will try to look at this later today.
>
> Cary
>
>
> On Monday, February 2, 2015 9:03 AM, Lonnie Gliem
> <lg...@sr...> wrote:
>
>
> Hi Cary, I found the code causing the error and have attahced a
> small verilog file that causes it.
>
> iverilog iverilog_core.v
>
> Then run it. [lgliem@ajax <mailto:lgliem@ajax> ulogic_sim]$
> ./a.out Fun: 0x7ba500 is for variable clk Fun: 0x7ba550 is for
> variable data_in_tmp Current vector
> is:32'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX New value
> is:33'bZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ vvp: vvp_net_sig.cc:185:
> virtual void vvp_fun_signal4_sa::recv_vec4(vvp_net_ptr_t, const
> vvp_vector4_t&, void**): Assertion `bit.size() == bits4_.size()'
> failed. Aborted (core dumped)
>
> Lonnie
>
>
>
>
>
>
>
> ------------------------------------------------------------------------------
>
>
Dive into the World of Parallel Programming. The Go Parallel Website,
> sponsored by Intel and developed in partnership with Slashdot
> Media, is your hub for all things parallel software development,
> from weekly thought leadership blogs to news, videos, case studies,
> tutorials and more. Take a look and join the conversation now.
> http://goparallel.sourceforge.net/
>
>
>
> _______________________________________________ Iverilog-devel
> mailing list Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>
- --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iEYEARECAAYFAlTQD18ACgkQrPt1Sc2b3inRWwCgtO8bBl+odSjaLxrskLw62HWU
F+8AoOuTKqoQMRyYVpPDtm7JD8yYYVrF
=qK5u
-----END PGP SIGNATURE-----
------------------------------------------------------------------------------
Dive into the World of Parallel Programming. The Go Parallel Website,
sponsored by Intel and developed in partnership with Slashdot Media, is your
hub for all things parallel software development, from weekly thought
leadership blogs to news, videos, case studies, tutorials and more. Take a
look and join the conversation now. http://goparallel.sourceforge.net/
_______________________________________________
Iverilog-devel mailing list
Ive...@li...
https://lists.sourceforge.net/lists/listinfo/iverilog-devel
|
|
From: Lonnie L G. <lg...@sr...> - 2015-02-03 14:56:05
|
Hi Cary,
How long until this fix will show up in a src.rpm?
Lonnie
From: Cary R. [mailto:cy...@ya...]
Sent: Monday, February 02, 2015 6:27 PM
To: Discussions concerning Icarus Verilog development
Subject: Re: [Iverilog-devel] vvp runtime error
Okay, there are still a few other issues since nested replications do not correctly check for a zero replication at a lower level which was why I thought I may have to keep the zero width check. (e.g. {{2{{0{sign}}}}, 16'h0001} should report that a zero width (zero replication) cannot be replicated. A zero replication is only allowed in a concatenation/replication if it is also included with another non-zero width element. There are likely other degenerate cases (e.g. {{0{sign}}, {0{lsb}}}, etc.) that need to be checked and reported in the compiler.
And then all this needs to be check for constant and non-constant values being replicated. Constant-constant is done in the compiler, constant-variable is done in the run time.
Cary
On Monday, February 2, 2015 4:00 PM, Stephen Williams <st...@ic...> wrote:
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
I kinda think this should be restricted to zero-replications,
and NOT zero-width expressions in general. I would rather catch
the latter is an error, or something.
On 02/02/2015 03:43 PM, Cary R. wrote:
> A patch for this has been pushed to git.
>
> The issues was that zero replications inside of concatenations
> were generating incorrect vvp code for the new stack based vector
> operators. For the moment this code checks to see if the
> sub-expression width is zero. A more specific fix would check to
> see if the sub-expression was a concatenation that had a zero
> replication. I can easily change the code if needed, but the zero
> width may be better if other things can also generate a zero width
> result. I don't know of any, but there may be SystemVerilog
> constructs that can do this. Does anyone have an opinion on this or
> know of a construct that can do this?
>
> Cary
>
>
> On Monday, February 2, 2015 10:20 AM, Cary R. <cy...@ya...>
> wrote:
>
>
> Hi Lonnie,
>
> I was able to reduce this example down even further. It looks like
> the problem is that when Steve switched to the new stack code
> something broke concerning zero replications. At the moment an
> input width of 32 is getting a sign bit added which gives a width
> of 33 instead of 32. I will try to look at this later today.
>
> Cary
>
>
> On Monday, February 2, 2015 9:03 AM, Lonnie Gliem
> <lg...@sr...> wrote:
>
>
> Hi Cary, I found the code causing the error and have attahced a
> small verilog file that causes it.
>
> iverilog iverilog_core.v
>
> Then run it. [lgliem@ajax <mailto:lgliem@ajax> ulogic_sim]$
> ./a.out Fun: 0x7ba500 is for variable clk Fun: 0x7ba550 is for
> variable data_in_tmp Current vector
> is:32'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX New value
> is:33'bZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ vvp: vvp_net_sig.cc:185:
> virtual void vvp_fun_signal4_sa::recv_vec4(vvp_net_ptr_t, const
> vvp_vector4_t&, void**): Assertion `bit.size() == bits4_.size()'
> failed. Aborted (core dumped)
>
> Lonnie
>
>
>
>
>
>
>
> ------------------------------------------------------------------------------
>
>
Dive into the World of Parallel Programming. The Go Parallel Website,
> sponsored by Intel and developed in partnership with Slashdot
> Media, is your hub for all things parallel software development,
> from weekly thought leadership blogs to news, videos, case studies,
> tutorials and more. Take a look and join the conversation now.
> http://goparallel.sourceforge.net/
>
>
>
> _______________________________________________ Iverilog-devel
> mailing list Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>
- --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com <http://www.icarus.com/> and lines to code before I sleep,
http://www.picturel.com <http://www.picturel.com/> And lines to code before I sleep."
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iEYEARECAAYFAlTQD18ACgkQrPt1Sc2b3inRWwCgtO8bBl+odSjaLxrskLw62HWU
F+8AoOuTKqoQMRyYVpPDtm7JD8yYYVrF
=qK5u
-----END PGP SIGNATURE-----
------------------------------------------------------------------------------
Dive into the World of Parallel Programming. The Go Parallel Website,
sponsored by Intel and developed in partnership with Slashdot Media, is your
hub for all things parallel software development, from weekly thought
leadership blogs to news, videos, case studies, tutorials and more. Take a
look and join the conversation now. http://goparallel.sourceforge.net/
_______________________________________________
Iverilog-devel mailing list
Ive...@li...
https://lists.sourceforge.net/lists/listinfo/iverilog-devel
|
|
From: Martin W. <mai...@ma...> - 2015-02-03 21:23:52
|
Cary R. wrote:
> Okay, there are still a few other issues since nested replications do not
> correctly check for a zero replication at a lower level which was why I
> thought I may have to keep the zero width check. (e.g. {{2{{0{sign}}}},
> 16'h0001} should report that a zero width (zero replication) cannot be
> replicated. A zero replication is only allowed in a
> concatenation/replication if it is also included with another non-zero
> width element. There are likely other degenerate cases (e.g. {{0{sign}},
> {0{lsb}}}, etc.) that need to be checked and reported in the compiler.
>
> And then all this needs to be check for constant and non-constant values
> being replicated. Constant-constant is done in the compiler,
> constant-variable is done in the run time. Cary
Another case that bypasses the zero replication check is a concatenation
within a concatenation, e.g. {a, b & {0{c}}}.
I'd try fixing the compiler check by using the elab_expr flags to flag
whether we are elaborating a singleton concatenation (I can have a go at this
if you don't have time).
Trying some other things, I find Icarus accepts a zero width literal number
(which isn't legal Verilog). It then gives different results for {a, 0'b0, b}
and {a, {0'b0}, b}. The first case is sensible (collapses to {a, b}), the
second case is not.
Martin
|
|
From: Lonnie L G. <lg...@sr...> - 2015-03-05 16:52:58
|
Hi Cary,
Do you know if this is in a snapshot yet. How can I check?
Thanks
Lonnie
From: Cary R. [mailto:cy...@ya...]
Sent: Monday, February 02, 2015 6:27 PM
To: Discussions concerning Icarus Verilog development
Subject: Re: [Iverilog-devel] vvp runtime error
Okay, there are still a few other issues since nested replications do not correctly check for a zero replication at a lower level which was why I thought I may have to keep the zero width check. (e.g. {{2{{0{sign}}}}, 16'h0001} should report that a zero width (zero replication) cannot be replicated. A zero replication is only allowed in a concatenation/replication if it is also included with another non-zero width element. There are likely other degenerate cases (e.g. {{0{sign}}, {0{lsb}}}, etc.) that need to be checked and reported in the compiler.
And then all this needs to be check for constant and non-constant values being replicated. Constant-constant is done in the compiler, constant-variable is done in the run time.
Cary
On Monday, February 2, 2015 4:00 PM, Stephen Williams <st...@ic...> wrote:
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
I kinda think this should be restricted to zero-replications,
and NOT zero-width expressions in general. I would rather catch
the latter is an error, or something.
On 02/02/2015 03:43 PM, Cary R. wrote:
> A patch for this has been pushed to git.
>
> The issues was that zero replications inside of concatenations
> were generating incorrect vvp code for the new stack based vector
> operators. For the moment this code checks to see if the
> sub-expression width is zero. A more specific fix would check to
> see if the sub-expression was a concatenation that had a zero
> replication. I can easily change the code if needed, but the zero
> width may be better if other things can also generate a zero width
> result. I don't know of any, but there may be SystemVerilog
> constructs that can do this. Does anyone have an opinion on this or
> know of a construct that can do this?
>
> Cary
>
>
> On Monday, February 2, 2015 10:20 AM, Cary R. <cy...@ya...>
> wrote:
>
>
> Hi Lonnie,
>
> I was able to reduce this example down even further. It looks like
> the problem is that when Steve switched to the new stack code
> something broke concerning zero replications. At the moment an
> input width of 32 is getting a sign bit added which gives a width
> of 33 instead of 32. I will try to look at this later today.
>
> Cary
>
>
> On Monday, February 2, 2015 9:03 AM, Lonnie Gliem
> <lg...@sr...> wrote:
>
>
> Hi Cary, I found the code causing the error and have attahced a
> small verilog file that causes it.
>
> iverilog iverilog_core.v
>
> Then run it. [lgliem@ajax <mailto:lgliem@ajax> ulogic_sim]$
> ./a.out Fun: 0x7ba500 is for variable clk Fun: 0x7ba550 is for
> variable data_in_tmp Current vector
> is:32'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX New value
> is:33'bZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ vvp: vvp_net_sig.cc:185:
> virtual void vvp_fun_signal4_sa::recv_vec4(vvp_net_ptr_t, const
> vvp_vector4_t&, void**): Assertion `bit.size() == bits4_.size()'
> failed. Aborted (core dumped)
>
> Lonnie
>
>
>
>
>
>
>
> ------------------------------------------------------------------------------
>
>
Dive into the World of Parallel Programming. The Go Parallel Website,
> sponsored by Intel and developed in partnership with Slashdot
> Media, is your hub for all things parallel software development,
> from weekly thought leadership blogs to news, videos, case studies,
> tutorials and more. Take a look and join the conversation now.
> http://goparallel.sourceforge.net/
>
>
>
> _______________________________________________ Iverilog-devel
> mailing list Ive...@li...
> https://lists.sourceforge.net/lists/listinfo/iverilog-devel
>
- --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com <http://www.icarus.com/> and lines to code before I sleep,
http://www.picturel.com <http://www.picturel.com/> And lines to code before I sleep."
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iEYEARECAAYFAlTQD18ACgkQrPt1Sc2b3inRWwCgtO8bBl+odSjaLxrskLw62HWU
F+8AoOuTKqoQMRyYVpPDtm7JD8yYYVrF
=qK5u
-----END PGP SIGNATURE-----
------------------------------------------------------------------------------
Dive into the World of Parallel Programming. The Go Parallel Website,
sponsored by Intel and developed in partnership with Slashdot Media, is your
hub for all things parallel software development, from weekly thought
leadership blogs to news, videos, case studies, tutorials and more. Take a
look and join the conversation now. http://goparallel.sourceforge.net/
_______________________________________________
Iverilog-devel mailing list
Ive...@li...
https://lists.sourceforge.net/lists/listinfo/iverilog-devel
|
|
From: Cary R. <cy...@ya...> - 2015-03-16 22:08:14
|
Hi Lonnie,
We have not done a snapshot since this was fixed. Steve normally announces snapshots when they are released and I believe he dates them so you would need to look for a snapshot that was newer than the one where you discovered the problem. There is also still one known issue related to zero-replications that I have not had time to research and verify what the correct fix is.
Cary
On Thursday, March 5, 2015 8:53 AM, Lonnie L Gliem <lg...@sr...> wrote:
#yiv7727319946 -- filtered {font-family:Helvetica;panose-1:2 11 6 4 2 2 2 2 2 4;}#yiv7727319946 filtered {font-family:Helvetica;panose-1:2 11 6 4 2 2 2 2 2 4;}#yiv7727319946 filtered {font-family:Calibri;panose-1:2 15 5 2 2 2 4 3 2 4;}#yiv7727319946 filtered {font-family:Tahoma;panose-1:2 11 6 4 3 5 4 4 2 4;}#yiv7727319946 p.yiv7727319946MsoNormal, #yiv7727319946 li.yiv7727319946MsoNormal, #yiv7727319946 div.yiv7727319946MsoNormal {margin:0in;margin-bottom:.0001pt;font-size:12.0pt;}#yiv7727319946 a:link, #yiv7727319946 span.yiv7727319946MsoHyperlink {color:blue;text-decoration:underline;}#yiv7727319946 a:visited, #yiv7727319946 span.yiv7727319946MsoHyperlinkFollowed {color:purple;text-decoration:underline;}#yiv7727319946 span.yiv7727319946EmailStyle17 {color:#1F497D;}#yiv7727319946 .yiv7727319946MsoChpDefault {font-size:10.0pt;}#yiv7727319946 filtered {margin:1.0in 1.0in 1.0in 1.0in;}#yiv7727319946 div.yiv7727319946WordSection1 {}#yiv7727319946 Hi Cary,Do you know if this is in a snapshot yet. How can I check?ThanksLonnie From: Cary R. [mailto:cy...@ya...]
Sent: Monday, February 02, 2015 6:27 PM
To: Discussions concerning Icarus Verilog development
Subject: Re: [Iverilog-devel] vvp runtime error Okay, there are still a few other issues since nested replications do not correctly check for a zero replication at a lower level which was why I thought I may have to keep the zero width check. (e.g. {{2{{0{sign}}}}, 16'h0001} should report that a zero width (zero replication) cannot be replicated. A zero replication is only allowed in a concatenation/replication if it is also included with another non-zero width element. There are likely other degenerate cases (e.g. {{0{sign}}, {0{lsb}}}, etc.) that need to be checked and reported in the compiler. And then all this needs to be check for constant and non-constant values being replicated. Constant-constant is done in the compiler, constant-variable is done in the run time. Cary On Monday, February 2, 2015 4:00 PM, Stephen Williams <st...@ic...> wrote: -----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
I kinda think this should be restricted to zero-replications,
and NOT zero-width expressions in general. I would rather catch
the latter is an error, or something.
On 02/02/2015 03:43 PM, Cary R. wrote:
> A patch for this has been pushed to git.
>
> The issues was that zero replications inside of concatenations
> were generating incorrect vvp code for the new stack based vector
> operators. For the moment this code checks to see if the
> sub-expression width is zero. A more specific fix would check to
> see if the sub-expression was a concatenation that had a zero
> replication. I can easily change the code if needed, but the zero
> width may be better if other things can also generate a zero width
> result. I don't know of any, but there may be SystemVerilog
> constructs that can do this. Does anyone have an opinion on this or
> know of a construct that can do this?
>
> Cary
>
>
> On Monday, February 2, 2015 10:20 AM, Cary R. <cy...@ya...>
> wrote:
>
>
> Hi Lonnie,
>
> I was able to reduce this example down even further. It looks like
> the problem is that when Steve switched to the new stack code
> something broke concerning zero replications. At the moment an
> input width of 32 is getting a sign bit added which gives a width
> of 33 instead of 32. I will try to look at this later today.
>
> Cary
>
>
> On Monday, February 2, 2015 9:03 AM, Lonnie Gliem
> <lg...@sr...> wrote:
>
>
> Hi Cary, I found the code causing the error and have attahced a
> small verilog file that causes it.
>
> iverilog iverilog_core.v
>
> Then run it. [lgliem@ajax <mailto:lgliem@ajax> ulogic_sim]$
> ./a.out Fun: 0x7ba500 is for variable clk Fun: 0x7ba550 is for
> variable data_in_tmp Current vector
> is:32'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX New value
> is:33'bZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ vvp: vvp_net_sig.cc:185:
> virtual void vvp_fun_signal4_sa::recv_vec4(vvp_net_ptr_t, const
> vvp_vector4_t&, void**): Assertion `bit.size() == bits4_.size()'
> failed. Aborted (core dumped)
>
> Lonnie
>
>
>
>
>
>
>
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- --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
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